NXP Semiconductors MKV56F22 2024.06.02 MKV56F22 Freescale Microcontroller CM7 r0p1 little true 4 false 8 32 ADC0 Analog-to-Digital Converter ADC0 0x0 0x0 0x70 registers n ADC0 37 CFG1 ADC Configuration Register 1 0x8 32 read-write n 0x0 0x0 ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 Alternate clock 2 (ALTCLK2) #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 ADIV Clock Divide Select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 Normal power configuration. #0 1 Low-power configuration. The power is reduced at the expense of maximum clock speed. #1 ADLSMP Sample Time Configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output #10 11 When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output #11 CFG2 ADC Configuration Register 2 0xC 32 read-write n 0x0 0x0 ADACKEN Asynchronous Clock Output Enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output is enabled regardless of the state of the ADC. #1 ADHSC High-Speed Configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. #1 ADLSTS Long Sample Time Select 0 2 read-write 00 Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 MUXSEL ADC Mux Select 4 1 read-write 0 ADxxa channels are selected. #0 1 ADxxb channels are selected. #1 CLM0 ADC Minus-Side General Calibration Value Register 0x6C 32 read-write n 0x0 0x0 CLM0 Calibration Value 0 6 read-write CLM1 ADC Minus-Side General Calibration Value Register 0x68 32 read-write n 0x0 0x0 CLM1 Calibration Value 0 7 read-write CLM2 ADC Minus-Side General Calibration Value Register 0x64 32 read-write n 0x0 0x0 CLM2 Calibration Value 0 8 read-write CLM3 ADC Minus-Side General Calibration Value Register 0x60 32 read-write n 0x0 0x0 CLM3 Calibration Value 0 9 read-write CLM4 ADC Minus-Side General Calibration Value Register 0x5C 32 read-write n 0x0 0x0 CLM4 Calibration Value 0 10 read-write CLMD ADC Minus-Side General Calibration Value Register 0x54 32 read-write n 0x0 0x0 CLMD Calibration Value 0 6 read-write CLMS ADC Minus-Side General Calibration Value Register 0x58 32 read-write n 0x0 0x0 CLMS Calibration Value 0 6 read-write CLP0 ADC Plus-Side General Calibration Value Register 0x4C 32 read-write n 0x0 0x0 CLP0 Calibration Value 0 6 read-write CLP1 ADC Plus-Side General Calibration Value Register 0x48 32 read-write n 0x0 0x0 CLP1 Calibration Value 0 7 read-write CLP2 ADC Plus-Side General Calibration Value Register 0x44 32 read-write n 0x0 0x0 CLP2 Calibration Value 0 8 read-write CLP3 ADC Plus-Side General Calibration Value Register 0x40 32 read-write n 0x0 0x0 CLP3 Calibration Value 0 9 read-write CLP4 ADC Plus-Side General Calibration Value Register 0x3C 32 read-write n 0x0 0x0 CLP4 Calibration Value 0 10 read-write CLPD ADC Plus-Side General Calibration Value Register 0x34 32 read-write n 0x0 0x0 CLPD Calibration Value 0 6 read-write CLPS ADC Plus-Side General Calibration Value Register 0x38 32 read-write n 0x0 0x0 CLPS Calibration Value 0 6 read-write CV1 Compare Value Registers 0x30 32 read-write n 0x0 0x0 CV Compare Value. 0 16 read-write CV2 Compare Value Registers 0x4C 32 read-write n 0x0 0x0 CV Compare Value. 0 16 read-write MG ADC Minus-Side Gain Register 0x30 32 read-write n 0x0 0x0 MG Minus-Side Gain 0 16 read-write OFS ADC Offset Correction Register 0x28 32 read-write n 0x0 0x0 OFS Offset Error Correction Value 0 16 read-write PG ADC Plus-Side Gain Register 0x2C 32 read-write n 0x0 0x0 PG Plus-Side Gain 0 16 read-write RA ADC Data Result Register 0x20 32 read-only n 0x0 0x0 D Data result 0 16 read-only RB ADC Data Result Register 0x34 32 read-only n 0x0 0x0 D Data result 0 16 read-only SC1A ADC Status and Control Registers 1 0x0 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11101 11110 When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. #11110 11111 Module is disabled. #11111 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt is disabled. #0 1 Conversion complete interrupt is enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion is not completed. #0 1 Conversion is completed. #1 DIFF Differential Mode Enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 SC1B ADC Status and Control Registers 1 0x4 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11101 11110 When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. #11110 11111 Module is disabled. #11111 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt is disabled. #0 1 Conversion complete interrupt is enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion is not completed. #0 1 Conversion is completed. #1 DIFF Differential Mode Enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 SC2 Status and Control Register 2 0x20 32 read-write n 0x0 0x0 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ACFGT Compare Function Greater Than Enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. #0 1 Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. #1 ACREN Compare Function Range Enable 3 1 read-write 0 Range function disabled. Only CV1 is compared. #0 1 Range function enabled. Both CV1 and CV2 are compared. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 DMAEN DMA Enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. #1 REFSEL Voltage Reference Selection 0 2 read-write 00 Default voltage reference pin pair, that is, external pins VREFH and VREFL #00 01 Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU #01 SC3 Status and Control Register 3 0x24 32 read-write n 0x0 0x0 ADCO Continuous Conversion Enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #1 AVGE Hardware Average Enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 AVGS Hardware Average Select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 CAL Calibration 7 1 read-write CALF Calibration Failed Flag 6 1 read-write 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 AIPS0 AIPS-Lite Bridge AIPS 0x0 0x0 0x70 registers n MPRA Master Privilege Register A 0x0 32 read-write n 0x0 0x0 MPL0 Master 0 Privilege Level 28 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL1 Master 1 Privilege Level 24 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL2 Master 2 Privilege Level 20 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL3 Master 3 Privilege Level 16 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTR0 Master 0 Trusted For Read 30 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR1 Master 1 Trusted for Read 26 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR2 Master 2 Trusted For Read 22 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR3 Master 3 Trusted For Read 18 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTW0 Master 0 Trusted For Writes 29 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW1 Master 1 Trusted for Writes 25 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW2 Master 2 Trusted For Writes 21 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW3 Master 3 Trusted For Writes 17 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 PACRA Peripheral Access Control Register 0x20 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRB Peripheral Access Control Register 0x24 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRC Peripheral Access Control Register 0x28 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRD Peripheral Access Control Register 0x2C 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRE Peripheral Access Control Register 0x40 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRF Peripheral Access Control Register 0x44 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRG Peripheral Access Control Register 0x48 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRH Peripheral Access Control Register 0x4C 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRI Peripheral Access Control Register 0x50 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRJ Peripheral Access Control Register 0x54 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRK Peripheral Access Control Register 0x58 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRL Peripheral Access Control Register 0x5C 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRM Peripheral Access Control Register 0x60 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRN Peripheral Access Control Register 0x64 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRO Peripheral Access Control Register 0x68 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRP Peripheral Access Control Register 0x6C 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 AIPS1 AIPS-Lite Bridge AIPS 0x0 0x0 0x70 registers n MPRA Master Privilege Register A 0x0 32 read-write n 0x0 0x0 MPL0 Master 0 Privilege Level 28 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL1 Master 1 Privilege Level 24 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL2 Master 2 Privilege Level 20 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL3 Master 3 Privilege Level 16 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTR0 Master 0 Trusted For Read 30 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR1 Master 1 Trusted for Read 26 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR2 Master 2 Trusted For Read 22 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR3 Master 3 Trusted For Read 18 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTW0 Master 0 Trusted For Writes 29 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW1 Master 1 Trusted for Writes 25 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW2 Master 2 Trusted For Writes 21 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW3 Master 3 Trusted For Writes 17 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 PACRA Peripheral Access Control Register 0x20 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRB Peripheral Access Control Register 0x24 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRC Peripheral Access Control Register 0x28 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRD Peripheral Access Control Register 0x2C 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRE Peripheral Access Control Register 0x40 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRF Peripheral Access Control Register 0x44 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRG Peripheral Access Control Register 0x48 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRH Peripheral Access Control Register 0x4C 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRI Peripheral Access Control Register 0x50 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRJ Peripheral Access Control Register 0x54 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRK Peripheral Access Control Register 0x58 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRL Peripheral Access Control Register 0x5C 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRM Peripheral Access Control Register 0x60 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRN Peripheral Access Control Register 0x64 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRO Peripheral Access Control Register 0x68 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRP Peripheral Access Control Register 0x6C 32 read-write n 0x0 0x0 SP0 Supervisor Protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor Protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor Protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor Protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor Protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor Protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor Protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor Protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted Protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted Protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted Protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted Protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted Protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted Protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted Protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted Protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write Protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write Protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write Protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write Protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write Protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write Protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write Protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write Protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 AOI0 AND/OR/INVERT module AOI0 0x0 0x0 0x10 registers n BFCRT010 Boolean Function Term 0 and 1 Configuration Register for EVENTn 0x0 16 read-write n 0x0 0x0 PT0_AC Product term 0, A input configuration 14 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT0_BC Product term 0, B input configuration 12 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT0_CC Product term 0, C input configuration 10 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT0_DC Product term 0, D input configuration 8 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 PT1_AC Product term 1, A input configuration 6 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT1_BC Product term 1, B input configuration 4 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT1_CC Product term 1, C input configuration 2 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT1_DC Product term 1, D input configuration 0 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 BFCRT011 Boolean Function Term 0 and 1 Configuration Register for EVENTn 0x4 16 read-write n 0x0 0x0 PT0_AC Product term 0, A input configuration 14 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT0_BC Product term 0, B input configuration 12 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT0_CC Product term 0, C input configuration 10 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT0_DC Product term 0, D input configuration 8 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 PT1_AC Product term 1, A input configuration 6 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT1_BC Product term 1, B input configuration 4 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT1_CC Product term 1, C input configuration 2 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT1_DC Product term 1, D input configuration 0 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 BFCRT012 Boolean Function Term 0 and 1 Configuration Register for EVENTn 0xC 16 read-write n 0x0 0x0 PT0_AC Product term 0, A input configuration 14 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT0_BC Product term 0, B input configuration 12 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT0_CC Product term 0, C input configuration 10 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT0_DC Product term 0, D input configuration 8 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 PT1_AC Product term 1, A input configuration 6 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT1_BC Product term 1, B input configuration 4 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT1_CC Product term 1, C input configuration 2 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT1_DC Product term 1, D input configuration 0 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 BFCRT013 Boolean Function Term 0 and 1 Configuration Register for EVENTn 0x18 16 read-write n 0x0 0x0 PT0_AC Product term 0, A input configuration 14 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT0_BC Product term 0, B input configuration 12 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT0_CC Product term 0, C input configuration 10 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT0_DC Product term 0, D input configuration 8 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 PT1_AC Product term 1, A input configuration 6 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT1_BC Product term 1, B input configuration 4 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT1_CC Product term 1, C input configuration 2 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT1_DC Product term 1, D input configuration 0 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 BFCRT230 Boolean Function Term 2 and 3 Configuration Register for EVENTn 0x4 16 read-write n 0x0 0x0 PT2_AC Product term 2, A input configuration 14 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT2_BC Product term 2, B input configuration 12 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT2_CC Product term 2, C input configuration 10 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT2_DC Product term 2, D input configuration 8 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 PT3_AC Product term 3, A input configuration 6 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT3_BC Product term 3, B input configuration 4 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT3_CC Product term 3, C input configuration 2 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT3_DC Product term 3, D input configuration 0 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 BFCRT231 Boolean Function Term 2 and 3 Configuration Register for EVENTn 0xA 16 read-write n 0x0 0x0 PT2_AC Product term 2, A input configuration 14 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT2_BC Product term 2, B input configuration 12 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT2_CC Product term 2, C input configuration 10 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT2_DC Product term 2, D input configuration 8 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 PT3_AC Product term 3, A input configuration 6 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT3_BC Product term 3, B input configuration 4 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT3_CC Product term 3, C input configuration 2 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT3_DC Product term 3, D input configuration 0 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 BFCRT232 Boolean Function Term 2 and 3 Configuration Register for EVENTn 0x14 16 read-write n 0x0 0x0 PT2_AC Product term 2, A input configuration 14 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT2_BC Product term 2, B input configuration 12 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT2_CC Product term 2, C input configuration 10 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT2_DC Product term 2, D input configuration 8 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 PT3_AC Product term 3, A input configuration 6 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT3_BC Product term 3, B input configuration 4 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT3_CC Product term 3, C input configuration 2 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT3_DC Product term 3, D input configuration 0 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 BFCRT233 Boolean Function Term 2 and 3 Configuration Register for EVENTn 0x22 16 read-write n 0x0 0x0 PT2_AC Product term 2, A input configuration 14 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT2_BC Product term 2, B input configuration 12 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT2_CC Product term 2, C input configuration 10 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT2_DC Product term 2, D input configuration 8 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 PT3_AC Product term 3, A input configuration 6 2 read-write 00 Force the A input in this product term to a logical zero #00 01 Pass the A input in this product term #01 10 Complement the A input in this product term #10 11 Force the A input in this product term to a logical one #11 PT3_BC Product term 3, B input configuration 4 2 read-write 00 Force the B input in this product term to a logical zero #00 01 Pass the B input in this product term #01 10 Complement the B input in this product term #10 11 Force the B input in this product term to a logical one #11 PT3_CC Product term 3, C input configuration 2 2 read-write 00 Force the C input in this product term to a logical zero #00 01 Pass the C input in this product term #01 10 Complement the C input in this product term #10 11 Force the C input in this product term to a logical one #11 PT3_DC Product term 3, D input configuration 0 2 read-write 00 Force the D input in this product term to a logical zero #00 01 Pass the D input in this product term #01 10 Complement the D input in this product term #10 11 Force the D input in this product term to a logical one #11 AXBS Crossbar switch AXBS 0x0 0x0 0xB04 registers n CRS0 Control Register 0x20 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 HLP Halt Low Priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 110 Park on master port M6 #110 111 Park on master port M7 #111 PCTL Parking Control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 RO Read Only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS1 Control Register 0x130 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 HLP Halt Low Priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 110 Park on master port M6 #110 111 Park on master port M7 #111 PCTL Parking Control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 RO Read Only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS2 Control Register 0x340 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 HLP Halt Low Priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 110 Park on master port M6 #110 111 Park on master port M7 #111 PCTL Parking Control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 RO Read Only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS3 Control Register 0x650 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 HLP Halt Low Priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 110 Park on master port M6 #110 111 Park on master port M7 #111 PCTL Parking Control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 RO Read Only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS4 Control Register 0xA60 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 HLP Halt Low Priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 110 Park on master port M6 #110 111 Park on master port M7 #111 PCTL Parking Control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 RO Read Only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS5 Control Register 0xF70 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 HLP Halt Low Priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 110 Park on master port M6 #110 111 Park on master port M7 #111 PCTL Parking Control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 RO Read Only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS6 Control Register 0x1580 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 HLP Halt Low Priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 110 Park on master port M6 #110 111 Park on master port M7 #111 PCTL Parking Control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 RO Read Only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 MGPCR0 Master General Purpose Control Register 0x1000 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 MGPCR1 Master General Purpose Control Register 0x1900 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 MGPCR2 Master General Purpose Control Register 0x2300 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 MGPCR3 Master General Purpose Control Register 0x2E00 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 PRS0 Priority Registers Slave 0x0 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 PRS1 Priority Registers Slave 0x100 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 PRS2 Priority Registers Slave 0x300 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 PRS3 Priority Registers Slave 0x600 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 PRS4 Priority Registers Slave 0xA00 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 PRS5 Priority Registers Slave 0xF00 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 PRS6 Priority Registers Slave 0x1500 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 CAN0 Flex Controller Area Network module CAN 0x0 0x0 0x8C0 registers n CAN0_ORed_Message_buffer 75 CAN0_Bus_Off 76 CAN0_Error 77 CAN0_Tx_Warning 78 CAN0_Rx_Warning 79 CAN0_Wake_Up 80 CBT CAN Bit Timing Register 0x50 32 read-write n 0x0 0x0 BTF Bit Timing Format Enable 31 1 read-write 0 Extended bit time definitions disabled. #0 1 Extended bit time definitions enabled. #1 EPRESDIV Extended Prescaler Division Factor 21 10 read-write EPROPSEG Extended Propagation Segment 10 6 read-write EPSEG1 Extended Phase Segment 1 5 5 read-write EPSEG2 Extended Phase Segment 2 0 5 read-write ERJW Extended Resync Jump Width 16 4 read-write CRCR CRC Register 0x44 32 read-only n 0x0 0x0 MBCRC CRC Mailbox 16 7 read-only TXCRC Transmitted CRC value 0 15 read-only CS0 Message Buffer 0 CS Register 0x80 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS1 Message Buffer 1 CS Register 0x90 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS10 Message Buffer 10 CS Register 0x120 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS11 Message Buffer 11 CS Register 0x130 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS12 Message Buffer 12 CS Register 0x140 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS13 Message Buffer 13 CS Register 0x150 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS14 Message Buffer 14 CS Register 0x160 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS15 Message Buffer 15 CS Register 0x170 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS2 Message Buffer 2 CS Register 0xA0 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS3 Message Buffer 3 CS Register 0xB0 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS4 Message Buffer 4 CS Register 0xC0 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS5 Message Buffer 5 CS Register 0xD0 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS6 Message Buffer 6 CS Register 0xE0 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS7 Message Buffer 7 CS Register 0xF0 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS8 Message Buffer 8 CS Register 0x100 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS9 Message Buffer 9 CS Register 0x110 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CTRL1 Control 1 register 0x4 32 read-write n 0x0 0x0 BOFFMSK Bus Off Interrupt Mask 15 1 read-write 0 Bus Off interrupt disabled. #0 1 Bus Off interrupt enabled. #1 BOFFREC Bus Off Recovery 6 1 read-write 0 Automatic recovering from Bus Off state enabled. #0 1 Automatic recovering from Bus Off state disabled. #1 CLKSRC CAN Engine Clock Source 13 1 read-write 0 The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. #0 1 The CAN engine clock source is the peripheral clock. #1 ERRMSK Error Interrupt Mask 14 1 read-write 0 Error interrupt disabled. #0 1 Error interrupt enabled. #1 LBUF Lowest Buffer Transmitted First 4 1 read-write 0 Buffer with highest priority is transmitted first. #0 1 Lowest number buffer is transmitted first. #1 LOM Listen-Only Mode 3 1 read-write 0 Listen-Only mode is deactivated. #0 1 FlexCAN module operates in Listen-Only mode. #1 LPB Loop Back Mode 12 1 read-write 0 Loop Back disabled. #0 1 Loop Back enabled. #1 PRESDIV Prescaler Division Factor 24 8 read-write PROPSEG Propagation Segment 0 3 read-write PSEG1 Phase Segment 1 19 3 read-write PSEG2 Phase Segment 2 16 3 read-write RJW Resync Jump Width 22 2 read-write RWRNMSK Rx Warning Interrupt Mask 10 1 read-write 0 Rx Warning Interrupt disabled. #0 1 Rx Warning Interrupt enabled. #1 SMP CAN Bit Sampling 7 1 read-write 0 Just one sample is used to determine the bit value. #0 1 Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used. #1 TSYN Timer Sync 5 1 read-write 0 Timer Sync feature disabled #0 1 Timer Sync feature enabled #1 TWRNMSK Tx Warning Interrupt Mask 11 1 read-write 0 Tx Warning Interrupt disabled. #0 1 Tx Warning Interrupt enabled. #1 CTRL2 Control 2 register 0x34 32 read-write n 0x0 0x0 BOFFDONEMSK Bus Off Done Interrupt Mask 30 1 read-write 0 Bus Off Done interrupt disabled. #0 1 Bus Off Done interrupt enabled. #1 EACEN Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 16 1 read-write 0 Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. #0 1 Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. #1 MRP Mailboxes Reception Priority 18 1 read-write 0 Matching starts from Rx FIFO and continues on Mailboxes. #0 1 Matching starts from Mailboxes and continues on Rx FIFO. #1 RFFN Number Of Rx FIFO Filters 24 4 read-write RRS Remote Request Storing 17 1 read-write 0 Remote Response Frame is generated. #0 1 Remote Request Frame is stored. #1 TASD Tx Arbitration Start Delay 19 5 read-write ECR Error Counter 0x1C 32 read-write n 0x0 0x0 RXERRCNT Receive Error Counter 8 8 read-write TXERRCNT Transmit Error Counter 0 8 read-write ESR1 Error and Status 1 register 0x20 32 read-write n 0x0 0x0 ACKERR Acknowledge Error 13 1 read-only 0 No such occurrence. #0 1 An ACK error occurred since last read of this register. #1 BIT0ERR Bit0 Error 14 1 read-only 0 No such occurrence. #0 1 At least one bit sent as dominant is received as recessive. #1 BIT1ERR Bit1 Error 15 1 read-only 0 No such occurrence. #0 1 At least one bit sent as recessive is received as dominant. #1 BOFFDONEINT Bus Off Done Interrupt 19 1 read-write 0 No such occurrence. #0 1 FlexCAN module has completed Bus Off process. #1 BOFFINT Bus Off Interrupt 2 1 read-write 0 No such occurrence. #0 1 FlexCAN module entered Bus Off state. #1 CRCERR Cyclic Redundancy Check Error 12 1 read-only 0 No such occurrence. #0 1 A CRC error occurred since last read of this register. #1 ERRINT Error Interrupt 1 1 read-write 0 No such occurrence. #0 1 Indicates setting of any Error Bit in the Error and Status Register. #1 ERROVR Error Overrun bit 21 1 read-write 0 Overrun has not occurred. #0 1 Overrun has occured. #1 FLTCONF Fault Confinement State 4 2 read-only 00 Error Active #00 01 Error Passive #01 1x Bus Off #1x FRMERR Form Error 11 1 read-only 0 No such occurrence. #0 1 A Form Error occurred since last read of this register. #1 IDLE This bit indicates when CAN bus is in IDLE state 7 1 read-only 0 No such occurrence. #0 1 CAN bus is now IDLE. #1 RWRNINT Rx Warning Interrupt Flag 16 1 read-write 0 No such occurrence. #0 1 The Rx error counter transitioned from less than 96 to greater than or equal to 96. #1 RX FlexCAN In Reception 3 1 read-only 0 FlexCAN is not receiving a message. #0 1 FlexCAN is receiving a message. #1 RXWRN Rx Error Warning 8 1 read-only 0 No such occurrence. #0 1 RXERRCNT is greater than or equal to 96. #1 STFERR Stuffing Error 10 1 read-only 0 No such occurrence. #0 1 A Stuffing Error occurred since last read of this register. #1 SYNCH CAN Synchronization Status 18 1 read-only 0 FlexCAN is not synchronized to the CAN bus. #0 1 FlexCAN is synchronized to the CAN bus. #1 TWRNINT Tx Warning Interrupt Flag 17 1 read-write 0 No such occurrence. #0 1 The Tx error counter transitioned from less than 96 to greater than or equal to 96. #1 TX FlexCAN In Transmission 6 1 read-only 0 FlexCAN is not transmitting a message. #0 1 FlexCAN is transmitting a message. #1 TXWRN TX Error Warning 9 1 read-only 0 No such occurrence. #0 1 TXERRCNT is greater than or equal to 96. #1 WAKINT Wake-Up Interrupt 0 1 read-write 0 No such occurrence. #0 1 Indicates a recessive to dominant transition was received on the CAN bus. #1 ESR2 Error and Status 2 register 0x38 32 read-only n 0x0 0x0 IMB Inactive Mailbox 13 1 read-only 0 If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. #0 1 If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. #1 LPTM Lowest Priority Tx Mailbox 16 7 read-only VPS Valid Priority Status 14 1 read-only 0 Contents of IMB and LPTM are invalid. #0 1 Contents of IMB and LPTM are valid. #1 ID0 Message Buffer 0 ID Register 0x84 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID1 Message Buffer 1 ID Register 0x94 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID10 Message Buffer 10 ID Register 0x124 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID11 Message Buffer 11 ID Register 0x134 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID12 Message Buffer 12 ID Register 0x144 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID13 Message Buffer 13 ID Register 0x154 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID14 Message Buffer 14 ID Register 0x164 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID15 Message Buffer 15 ID Register 0x174 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID2 Message Buffer 2 ID Register 0xA4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID3 Message Buffer 3 ID Register 0xB4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID4 Message Buffer 4 ID Register 0xC4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID5 Message Buffer 5 ID Register 0xD4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID6 Message Buffer 6 ID Register 0xE4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID7 Message Buffer 7 ID Register 0xF4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID8 Message Buffer 8 ID Register 0x104 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID9 Message Buffer 9 ID Register 0x114 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write IFLAG1 Interrupt Flags 1 register 0x30 32 read-write n 0x0 0x0 BUF0I Buffer MB0 Interrupt Or Clear FIFO bit 0 1 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. #0 1 The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. #1 BUF31TO8I Buffer MBi Interrupt 8 24 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception. #0 1 The corresponding buffer has successfully completed transmission or reception. #1 BUF4TO1I Buffer MB i Interrupt Or "reserved" 1 4 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. #0000 1 The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. #0001 BUF5I Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 5 1 read-write 0 No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 #0 1 MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. #1 BUF6I Buffer MB6 Interrupt Or "Rx FIFO Warning" 6 1 read-write 0 No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 #0 1 MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 #1 BUF7I Buffer MB7 Interrupt Or "Rx FIFO Overflow" 7 1 read-write 0 No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 #0 1 MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 #1 IMASK1 Interrupt Masks 1 register 0x28 32 read-write n 0x0 0x0 BUF31TO0M Buffer MB i Mask 0 32 read-write 0 The corresponding buffer Interrupt is disabled. #0 1 The corresponding buffer Interrupt is enabled. #1 MCR Module Configuration Register 0x0 32 read-write n 0x0 0x0 AEN Abort Enable 12 1 read-write 0 Abort disabled. #0 1 Abort enabled. #1 DMA DMA Enable 15 1 read-write 0 DMA feature for RX FIFO disabled. #0 1 DMA feature for RX FIFO enabled. #1 DOZE Doze Mode Enable 18 1 read-write 0 FlexCAN is not enabled to enter low-power mode when Doze mode is requested. #0 1 FlexCAN is enabled to enter low-power mode when Doze mode is requested. #1 FRZ Freeze Enable 30 1 read-write 0 Not enabled to enter Freeze mode. #0 1 Enabled to enter Freeze mode. #1 FRZACK Freeze Mode Acknowledge 24 1 read-only 0 FlexCAN not in Freeze mode, prescaler running. #0 1 FlexCAN in Freeze mode, prescaler stopped. #1 HALT Halt FlexCAN 28 1 read-write 0 No Freeze mode request. #0 1 Enters Freeze mode if the FRZ bit is asserted. #1 IDAM ID Acceptance Mode 8 2 read-write 00 Format A: One full ID (standard and extended) per ID Filter Table element. #00 01 Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. #01 10 Format C: Four partial 8-bit Standard IDs per ID Filter Table element. #10 11 Format D: All frames rejected. #11 IRMQ Individual Rx Masking And Queue Enable 16 1 read-write 0 Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. #0 1 Individual Rx masking and queue feature are enabled. #1 LPMACK Low-Power Mode Acknowledge 20 1 read-only 0 FlexCAN is not in a low-power mode. #0 1 FlexCAN is in a low-power mode. #1 LPRIOEN Local Priority Enable 13 1 read-write 0 Local Priority disabled. #0 1 Local Priority enabled. #1 MAXMB Number Of The Last Message Buffer 0 7 read-write MDIS Module Disable 31 1 read-write 0 Enable the FlexCAN module. #0 1 Disable the FlexCAN module. #1 NOTRDY FlexCAN Not Ready 27 1 read-only 0 FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. #0 1 FlexCAN module is either in Disable mode, Doze mode , Stop mode or Freeze mode. #1 RFEN Rx FIFO Enable 29 1 read-write 0 Rx FIFO not enabled. #0 1 Rx FIFO enabled. #1 SLFWAK Self Wake Up 22 1 read-write 0 FlexCAN Self Wake Up feature is disabled. #0 1 FlexCAN Self Wake Up feature is enabled. #1 SOFTRST Soft Reset 25 1 read-write 0 No reset request. #0 1 Resets the registers affected by soft reset. #1 SRXDIS Self Reception Disable 17 1 read-write 0 Self reception enabled. #0 1 Self reception disabled. #1 SUPV Supervisor Mode 23 1 read-write 0 FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. #0 1 FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. #1 WAKMSK Wake Up Interrupt Mask 26 1 read-write 0 Wake Up Interrupt is disabled. #0 1 Wake Up Interrupt is enabled. #1 WAKSRC Wake Up Source 19 1 read-write 0 FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. #0 1 FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. #1 WRNEN Warning Interrupt Enable 21 1 read-write 0 TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. #0 1 TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. #1 RX14MASK Rx 14 Mask register 0x14 32 read-write n 0x0 0x0 RX14M Rx Buffer 14 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RX15MASK Rx 15 Mask register 0x18 32 read-write n 0x0 0x0 RX15M Rx Buffer 15 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXFGMASK Rx FIFO Global Mask register 0x48 32 read-write n 0x0 0x0 FGM Rx FIFO Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXFIR Rx FIFO Information Register 0x4C 32 read-only n 0x0 0x0 IDHIT Identifier Acceptance Filter Hit Indicator 0 9 read-only RXIMR0 Rx Individual Mask Registers 0x1100 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR1 Rx Individual Mask Registers 0x1984 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR10 Rx Individual Mask Registers 0x66DC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR11 Rx Individual Mask Registers 0x6F88 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR12 Rx Individual Mask Registers 0x7838 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR13 Rx Individual Mask Registers 0x80EC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR14 Rx Individual Mask Registers 0x89A4 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR15 Rx Individual Mask Registers 0x9260 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR2 Rx Individual Mask Registers 0x220C 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR3 Rx Individual Mask Registers 0x2A98 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR4 Rx Individual Mask Registers 0x3328 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR5 Rx Individual Mask Registers 0x3BBC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR6 Rx Individual Mask Registers 0x4454 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR7 Rx Individual Mask Registers 0x4CF0 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR8 Rx Individual Mask Registers 0x5590 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR9 Rx Individual Mask Registers 0x5E34 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXMGMASK Rx Mailboxes Global Mask Register 0x10 32 read-write n 0x0 0x0 MG Rx Mailboxes Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 TIMER Free Running Timer 0x8 32 read-write n 0x0 0x0 TIMER Timer Value 0 16 read-write WORD00 Message Buffer 0 WORD0 Register 0x88 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD01 Message Buffer 1 WORD0 Register 0x98 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD010 Message Buffer 10 WORD0 Register 0x128 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD011 Message Buffer 11 WORD0 Register 0x138 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD012 Message Buffer 12 WORD0 Register 0x148 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD013 Message Buffer 13 WORD0 Register 0x158 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD014 Message Buffer 14 WORD0 Register 0x168 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD015 Message Buffer 15 WORD0 Register 0x178 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD02 Message Buffer 2 WORD0 Register 0xA8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD03 Message Buffer 3 WORD0 Register 0xB8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD04 Message Buffer 4 WORD0 Register 0xC8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD05 Message Buffer 5 WORD0 Register 0xD8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD06 Message Buffer 6 WORD0 Register 0xE8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD07 Message Buffer 7 WORD0 Register 0xF8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD08 Message Buffer 8 WORD0 Register 0x108 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD09 Message Buffer 9 WORD0 Register 0x118 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD10 Message Buffer 0 WORD1 Register 0x8C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD11 Message Buffer 1 WORD1 Register 0x9C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD110 Message Buffer 10 WORD1 Register 0x12C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD111 Message Buffer 11 WORD1 Register 0x13C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD112 Message Buffer 12 WORD1 Register 0x14C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD113 Message Buffer 13 WORD1 Register 0x15C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD114 Message Buffer 14 WORD1 Register 0x16C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD115 Message Buffer 15 WORD1 Register 0x17C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD12 Message Buffer 2 WORD1 Register 0xAC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD13 Message Buffer 3 WORD1 Register 0xBC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD14 Message Buffer 4 WORD1 Register 0xCC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD15 Message Buffer 5 WORD1 Register 0xDC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD16 Message Buffer 6 WORD1 Register 0xEC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD17 Message Buffer 7 WORD1 Register 0xFC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD18 Message Buffer 8 WORD1 Register 0x10C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD19 Message Buffer 9 WORD1 Register 0x11C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write CAN1 Flex Controller Area Network module CAN 0x0 0x0 0x8C0 registers n CAN1_ORed_Message_buffer 94 CAN1_Bus_Off 95 CAN1_Error 96 CAN1_Tx_Warning 97 CAN1_Rx_Warning 98 CAN1_Wake_Up 99 CBT CAN Bit Timing Register 0x50 32 read-write n 0x0 0x0 BTF Bit Timing Format Enable 31 1 read-write 0 Extended bit time definitions disabled. #0 1 Extended bit time definitions enabled. #1 EPRESDIV Extended Prescaler Division Factor 21 10 read-write EPROPSEG Extended Propagation Segment 10 6 read-write EPSEG1 Extended Phase Segment 1 5 5 read-write EPSEG2 Extended Phase Segment 2 0 5 read-write ERJW Extended Resync Jump Width 16 4 read-write CRCR CRC Register 0x44 32 read-only n 0x0 0x0 MBCRC CRC Mailbox 16 7 read-only TXCRC Transmitted CRC value 0 15 read-only CS0 Message Buffer 0 CS Register 0x80 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS1 Message Buffer 1 CS Register 0x90 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS10 Message Buffer 10 CS Register 0x120 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS11 Message Buffer 11 CS Register 0x130 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS12 Message Buffer 12 CS Register 0x140 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS13 Message Buffer 13 CS Register 0x150 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS14 Message Buffer 14 CS Register 0x160 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS15 Message Buffer 15 CS Register 0x170 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS2 Message Buffer 2 CS Register 0xA0 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS3 Message Buffer 3 CS Register 0xB0 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS4 Message Buffer 4 CS Register 0xC0 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS5 Message Buffer 5 CS Register 0xD0 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS6 Message Buffer 6 CS Register 0xE0 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS7 Message Buffer 7 CS Register 0xF0 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS8 Message Buffer 8 CS Register 0x100 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS9 Message Buffer 9 CS Register 0x110 32 read-write n 0x0 0x0 BRS Reserved 30 1 read-write CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write EDL Reserved 31 1 read-write ESI Reserved 29 1 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CTRL1 Control 1 register 0x4 32 read-write n 0x0 0x0 BOFFMSK Bus Off Interrupt Mask 15 1 read-write 0 Bus Off interrupt disabled. #0 1 Bus Off interrupt enabled. #1 BOFFREC Bus Off Recovery 6 1 read-write 0 Automatic recovering from Bus Off state enabled. #0 1 Automatic recovering from Bus Off state disabled. #1 CLKSRC CAN Engine Clock Source 13 1 read-write 0 The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. #0 1 The CAN engine clock source is the peripheral clock. #1 ERRMSK Error Interrupt Mask 14 1 read-write 0 Error interrupt disabled. #0 1 Error interrupt enabled. #1 LBUF Lowest Buffer Transmitted First 4 1 read-write 0 Buffer with highest priority is transmitted first. #0 1 Lowest number buffer is transmitted first. #1 LOM Listen-Only Mode 3 1 read-write 0 Listen-Only mode is deactivated. #0 1 FlexCAN module operates in Listen-Only mode. #1 LPB Loop Back Mode 12 1 read-write 0 Loop Back disabled. #0 1 Loop Back enabled. #1 PRESDIV Prescaler Division Factor 24 8 read-write PROPSEG Propagation Segment 0 3 read-write PSEG1 Phase Segment 1 19 3 read-write PSEG2 Phase Segment 2 16 3 read-write RJW Resync Jump Width 22 2 read-write RWRNMSK Rx Warning Interrupt Mask 10 1 read-write 0 Rx Warning Interrupt disabled. #0 1 Rx Warning Interrupt enabled. #1 SMP CAN Bit Sampling 7 1 read-write 0 Just one sample is used to determine the bit value. #0 1 Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used. #1 TSYN Timer Sync 5 1 read-write 0 Timer Sync feature disabled #0 1 Timer Sync feature enabled #1 TWRNMSK Tx Warning Interrupt Mask 11 1 read-write 0 Tx Warning Interrupt disabled. #0 1 Tx Warning Interrupt enabled. #1 CTRL2 Control 2 register 0x34 32 read-write n 0x0 0x0 BOFFDONEMSK Bus Off Done Interrupt Mask 30 1 read-write 0 Bus Off Done interrupt disabled. #0 1 Bus Off Done interrupt enabled. #1 EACEN Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 16 1 read-write 0 Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. #0 1 Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. #1 MRP Mailboxes Reception Priority 18 1 read-write 0 Matching starts from Rx FIFO and continues on Mailboxes. #0 1 Matching starts from Mailboxes and continues on Rx FIFO. #1 RFFN Number Of Rx FIFO Filters 24 4 read-write RRS Remote Request Storing 17 1 read-write 0 Remote Response Frame is generated. #0 1 Remote Request Frame is stored. #1 TASD Tx Arbitration Start Delay 19 5 read-write ECR Error Counter 0x1C 32 read-write n 0x0 0x0 RXERRCNT Receive Error Counter 8 8 read-write TXERRCNT Transmit Error Counter 0 8 read-write ESR1 Error and Status 1 register 0x20 32 read-write n 0x0 0x0 ACKERR Acknowledge Error 13 1 read-only 0 No such occurrence. #0 1 An ACK error occurred since last read of this register. #1 BIT0ERR Bit0 Error 14 1 read-only 0 No such occurrence. #0 1 At least one bit sent as dominant is received as recessive. #1 BIT1ERR Bit1 Error 15 1 read-only 0 No such occurrence. #0 1 At least one bit sent as recessive is received as dominant. #1 BOFFDONEINT Bus Off Done Interrupt 19 1 read-write 0 No such occurrence. #0 1 FlexCAN module has completed Bus Off process. #1 BOFFINT Bus Off Interrupt 2 1 read-write 0 No such occurrence. #0 1 FlexCAN module entered Bus Off state. #1 CRCERR Cyclic Redundancy Check Error 12 1 read-only 0 No such occurrence. #0 1 A CRC error occurred since last read of this register. #1 ERRINT Error Interrupt 1 1 read-write 0 No such occurrence. #0 1 Indicates setting of any Error Bit in the Error and Status Register. #1 ERROVR Error Overrun bit 21 1 read-write 0 Overrun has not occurred. #0 1 Overrun has occured. #1 FLTCONF Fault Confinement State 4 2 read-only 00 Error Active #00 01 Error Passive #01 1x Bus Off #1x FRMERR Form Error 11 1 read-only 0 No such occurrence. #0 1 A Form Error occurred since last read of this register. #1 IDLE This bit indicates when CAN bus is in IDLE state 7 1 read-only 0 No such occurrence. #0 1 CAN bus is now IDLE. #1 RWRNINT Rx Warning Interrupt Flag 16 1 read-write 0 No such occurrence. #0 1 The Rx error counter transitioned from less than 96 to greater than or equal to 96. #1 RX FlexCAN In Reception 3 1 read-only 0 FlexCAN is not receiving a message. #0 1 FlexCAN is receiving a message. #1 RXWRN Rx Error Warning 8 1 read-only 0 No such occurrence. #0 1 RXERRCNT is greater than or equal to 96. #1 STFERR Stuffing Error 10 1 read-only 0 No such occurrence. #0 1 A Stuffing Error occurred since last read of this register. #1 SYNCH CAN Synchronization Status 18 1 read-only 0 FlexCAN is not synchronized to the CAN bus. #0 1 FlexCAN is synchronized to the CAN bus. #1 TWRNINT Tx Warning Interrupt Flag 17 1 read-write 0 No such occurrence. #0 1 The Tx error counter transitioned from less than 96 to greater than or equal to 96. #1 TX FlexCAN In Transmission 6 1 read-only 0 FlexCAN is not transmitting a message. #0 1 FlexCAN is transmitting a message. #1 TXWRN TX Error Warning 9 1 read-only 0 No such occurrence. #0 1 TXERRCNT is greater than or equal to 96. #1 WAKINT Wake-Up Interrupt 0 1 read-write 0 No such occurrence. #0 1 Indicates a recessive to dominant transition was received on the CAN bus. #1 ESR2 Error and Status 2 register 0x38 32 read-only n 0x0 0x0 IMB Inactive Mailbox 13 1 read-only 0 If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. #0 1 If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. #1 LPTM Lowest Priority Tx Mailbox 16 7 read-only VPS Valid Priority Status 14 1 read-only 0 Contents of IMB and LPTM are invalid. #0 1 Contents of IMB and LPTM are valid. #1 ID0 Message Buffer 0 ID Register 0x84 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID1 Message Buffer 1 ID Register 0x94 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID10 Message Buffer 10 ID Register 0x124 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID11 Message Buffer 11 ID Register 0x134 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID12 Message Buffer 12 ID Register 0x144 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID13 Message Buffer 13 ID Register 0x154 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID14 Message Buffer 14 ID Register 0x164 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID15 Message Buffer 15 ID Register 0x174 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID2 Message Buffer 2 ID Register 0xA4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID3 Message Buffer 3 ID Register 0xB4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID4 Message Buffer 4 ID Register 0xC4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID5 Message Buffer 5 ID Register 0xD4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID6 Message Buffer 6 ID Register 0xE4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID7 Message Buffer 7 ID Register 0xF4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID8 Message Buffer 8 ID Register 0x104 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID9 Message Buffer 9 ID Register 0x114 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write IFLAG1 Interrupt Flags 1 register 0x30 32 read-write n 0x0 0x0 BUF0I Buffer MB0 Interrupt Or Clear FIFO bit 0 1 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. #0 1 The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. #1 BUF31TO8I Buffer MBi Interrupt 8 24 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception. #0 1 The corresponding buffer has successfully completed transmission or reception. #1 BUF4TO1I Buffer MB i Interrupt Or "reserved" 1 4 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. #0000 1 The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. #0001 BUF5I Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 5 1 read-write 0 No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 #0 1 MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. #1 BUF6I Buffer MB6 Interrupt Or "Rx FIFO Warning" 6 1 read-write 0 No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 #0 1 MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 #1 BUF7I Buffer MB7 Interrupt Or "Rx FIFO Overflow" 7 1 read-write 0 No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 #0 1 MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 #1 IMASK1 Interrupt Masks 1 register 0x28 32 read-write n 0x0 0x0 BUF31TO0M Buffer MB i Mask 0 32 read-write 0 The corresponding buffer Interrupt is disabled. #0 1 The corresponding buffer Interrupt is enabled. #1 MCR Module Configuration Register 0x0 32 read-write n 0x0 0x0 AEN Abort Enable 12 1 read-write 0 Abort disabled. #0 1 Abort enabled. #1 DMA DMA Enable 15 1 read-write 0 DMA feature for RX FIFO disabled. #0 1 DMA feature for RX FIFO enabled. #1 DOZE Doze Mode Enable 18 1 read-write 0 FlexCAN is not enabled to enter low-power mode when Doze mode is requested. #0 1 FlexCAN is enabled to enter low-power mode when Doze mode is requested. #1 FRZ Freeze Enable 30 1 read-write 0 Not enabled to enter Freeze mode. #0 1 Enabled to enter Freeze mode. #1 FRZACK Freeze Mode Acknowledge 24 1 read-only 0 FlexCAN not in Freeze mode, prescaler running. #0 1 FlexCAN in Freeze mode, prescaler stopped. #1 HALT Halt FlexCAN 28 1 read-write 0 No Freeze mode request. #0 1 Enters Freeze mode if the FRZ bit is asserted. #1 IDAM ID Acceptance Mode 8 2 read-write 00 Format A: One full ID (standard and extended) per ID Filter Table element. #00 01 Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. #01 10 Format C: Four partial 8-bit Standard IDs per ID Filter Table element. #10 11 Format D: All frames rejected. #11 IRMQ Individual Rx Masking And Queue Enable 16 1 read-write 0 Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. #0 1 Individual Rx masking and queue feature are enabled. #1 LPMACK Low-Power Mode Acknowledge 20 1 read-only 0 FlexCAN is not in a low-power mode. #0 1 FlexCAN is in a low-power mode. #1 LPRIOEN Local Priority Enable 13 1 read-write 0 Local Priority disabled. #0 1 Local Priority enabled. #1 MAXMB Number Of The Last Message Buffer 0 7 read-write MDIS Module Disable 31 1 read-write 0 Enable the FlexCAN module. #0 1 Disable the FlexCAN module. #1 NOTRDY FlexCAN Not Ready 27 1 read-only 0 FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. #0 1 FlexCAN module is either in Disable mode, Doze mode , Stop mode or Freeze mode. #1 RFEN Rx FIFO Enable 29 1 read-write 0 Rx FIFO not enabled. #0 1 Rx FIFO enabled. #1 SLFWAK Self Wake Up 22 1 read-write 0 FlexCAN Self Wake Up feature is disabled. #0 1 FlexCAN Self Wake Up feature is enabled. #1 SOFTRST Soft Reset 25 1 read-write 0 No reset request. #0 1 Resets the registers affected by soft reset. #1 SRXDIS Self Reception Disable 17 1 read-write 0 Self reception enabled. #0 1 Self reception disabled. #1 SUPV Supervisor Mode 23 1 read-write 0 FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. #0 1 FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. #1 WAKMSK Wake Up Interrupt Mask 26 1 read-write 0 Wake Up Interrupt is disabled. #0 1 Wake Up Interrupt is enabled. #1 WAKSRC Wake Up Source 19 1 read-write 0 FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. #0 1 FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. #1 WRNEN Warning Interrupt Enable 21 1 read-write 0 TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. #0 1 TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. #1 RX14MASK Rx 14 Mask register 0x14 32 read-write n 0x0 0x0 RX14M Rx Buffer 14 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RX15MASK Rx 15 Mask register 0x18 32 read-write n 0x0 0x0 RX15M Rx Buffer 15 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXFGMASK Rx FIFO Global Mask register 0x48 32 read-write n 0x0 0x0 FGM Rx FIFO Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXFIR Rx FIFO Information Register 0x4C 32 read-only n 0x0 0x0 IDHIT Identifier Acceptance Filter Hit Indicator 0 9 read-only RXIMR0 Rx Individual Mask Registers 0x1100 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR1 Rx Individual Mask Registers 0x1984 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR10 Rx Individual Mask Registers 0x66DC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR11 Rx Individual Mask Registers 0x6F88 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR12 Rx Individual Mask Registers 0x7838 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR13 Rx Individual Mask Registers 0x80EC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR14 Rx Individual Mask Registers 0x89A4 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR15 Rx Individual Mask Registers 0x9260 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR2 Rx Individual Mask Registers 0x220C 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR3 Rx Individual Mask Registers 0x2A98 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR4 Rx Individual Mask Registers 0x3328 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR5 Rx Individual Mask Registers 0x3BBC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR6 Rx Individual Mask Registers 0x4454 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR7 Rx Individual Mask Registers 0x4CF0 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR8 Rx Individual Mask Registers 0x5590 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR9 Rx Individual Mask Registers 0x5E34 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXMGMASK Rx Mailboxes Global Mask Register 0x10 32 read-write n 0x0 0x0 MG Rx Mailboxes Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 TIMER Free Running Timer 0x8 32 read-write n 0x0 0x0 TIMER Timer Value 0 16 read-write WORD00 Message Buffer 0 WORD0 Register 0x88 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD01 Message Buffer 1 WORD0 Register 0x98 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD010 Message Buffer 10 WORD0 Register 0x128 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD011 Message Buffer 11 WORD0 Register 0x138 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD012 Message Buffer 12 WORD0 Register 0x148 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD013 Message Buffer 13 WORD0 Register 0x158 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD014 Message Buffer 14 WORD0 Register 0x168 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD015 Message Buffer 15 WORD0 Register 0x178 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD02 Message Buffer 2 WORD0 Register 0xA8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD03 Message Buffer 3 WORD0 Register 0xB8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD04 Message Buffer 4 WORD0 Register 0xC8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD05 Message Buffer 5 WORD0 Register 0xD8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD06 Message Buffer 6 WORD0 Register 0xE8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD07 Message Buffer 7 WORD0 Register 0xF8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD08 Message Buffer 8 WORD0 Register 0x108 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD09 Message Buffer 9 WORD0 Register 0x118 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD10 Message Buffer 0 WORD1 Register 0x8C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD11 Message Buffer 1 WORD1 Register 0x9C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD110 Message Buffer 10 WORD1 Register 0x12C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD111 Message Buffer 11 WORD1 Register 0x13C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD112 Message Buffer 12 WORD1 Register 0x14C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD113 Message Buffer 13 WORD1 Register 0x15C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD114 Message Buffer 14 WORD1 Register 0x16C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD115 Message Buffer 15 WORD1 Register 0x17C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD12 Message Buffer 2 WORD1 Register 0xAC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD13 Message Buffer 3 WORD1 Register 0xBC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD14 Message Buffer 4 WORD1 Register 0xCC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD15 Message Buffer 5 WORD1 Register 0xDC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD16 Message Buffer 6 WORD1 Register 0xEC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD17 Message Buffer 7 WORD1 Register 0xFC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD18 Message Buffer 8 WORD1 Register 0x10C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD19 Message Buffer 9 WORD1 Register 0x11C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write CAU Memory Mapped Cryptographic Acceleration Unit (MMCAU) CAU 0x0 0x0 0xB6C registers n ADR_CA0 General Purpose Register 0 - Add to register command 0x8C8 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only ADR_CA1 General Purpose Register 1 - Add to register command 0x8CC 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only ADR_CA2 General Purpose Register 2 - Add to register command 0x8D0 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only ADR_CA3 General Purpose Register 3 - Add to register command 0x8D4 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only ADR_CA4 General Purpose Register 4 - Add to register command 0x8D8 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only ADR_CA5 General Purpose Register 5 - Add to register command 0x8DC 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only ADR_CA6 General Purpose Register 6 - Add to register command 0x8E0 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only ADR_CA7 General Purpose Register 7 - Add to register command 0x8E4 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only ADR_CA8 General Purpose Register 8 - Add to register command 0x8E8 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only ADR_CAA Accumulator register - Add to register command 0x8C4 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only ADR_CASR Status register - Add Register command 0x8C0 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 AESC_CA0 General Purpose Register 0 - AES Column Operation command 0xB08 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only AESC_CA1 General Purpose Register 1 - AES Column Operation command 0xB0C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only AESC_CA2 General Purpose Register 2 - AES Column Operation command 0xB10 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only AESC_CA3 General Purpose Register 3 - AES Column Operation command 0xB14 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only AESC_CA4 General Purpose Register 4 - AES Column Operation command 0xB18 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only AESC_CA5 General Purpose Register 5 - AES Column Operation command 0xB1C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only AESC_CA6 General Purpose Register 6 - AES Column Operation command 0xB20 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only AESC_CA7 General Purpose Register 7 - AES Column Operation command 0xB24 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only AESC_CA8 General Purpose Register 8 - AES Column Operation command 0xB28 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only AESC_CAA Accumulator register - AES Column Operation command 0xB04 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only AESC_CASR Status register - AES Column Operation command 0xB00 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 AESIC_CA0 General Purpose Register 0 - AES Inverse Column Operation command 0xB48 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only AESIC_CA1 General Purpose Register 1 - AES Inverse Column Operation command 0xB4C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only AESIC_CA2 General Purpose Register 2 - AES Inverse Column Operation command 0xB50 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only AESIC_CA3 General Purpose Register 3 - AES Inverse Column Operation command 0xB54 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only AESIC_CA4 General Purpose Register 4 - AES Inverse Column Operation command 0xB58 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only AESIC_CA5 General Purpose Register 5 - AES Inverse Column Operation command 0xB5C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only AESIC_CA6 General Purpose Register 6 - AES Inverse Column Operation command 0xB60 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only AESIC_CA7 General Purpose Register 7 - AES Inverse Column Operation command 0xB64 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only AESIC_CA8 General Purpose Register 8 - AES Inverse Column Operation command 0xB68 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only AESIC_CAA Accumulator register - AES Inverse Column Operation command 0xB44 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only AESIC_CASR Status register - AES Inverse Column Operation command 0xB40 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 DIRECT0 Direct access register 0 0x0 32 write-only n 0x0 0x0 CAU_DIRECT0 Direct register 0 0 32 write-only DIRECT1 Direct access register 1 0x4 32 write-only n 0x0 0x0 CAU_DIRECT1 Direct register 1 0 32 write-only DIRECT10 Direct access register 10 0x28 32 write-only n 0x0 0x0 CAU_DIRECT10 Direct register 10 0 32 write-only DIRECT11 Direct access register 11 0x2C 32 write-only n 0x0 0x0 CAU_DIRECT11 Direct register 11 0 32 write-only DIRECT12 Direct access register 12 0x30 32 write-only n 0x0 0x0 CAU_DIRECT12 Direct register 12 0 32 write-only DIRECT13 Direct access register 13 0x34 32 write-only n 0x0 0x0 CAU_DIRECT13 Direct register 13 0 32 write-only DIRECT14 Direct access register 14 0x38 32 write-only n 0x0 0x0 CAU_DIRECT14 Direct register 14 0 32 write-only DIRECT15 Direct access register 15 0x3C 32 write-only n 0x0 0x0 CAU_DIRECT15 Direct register 15 0 32 write-only DIRECT2 Direct access register 2 0x8 32 write-only n 0x0 0x0 CAU_DIRECT2 Direct register 2 0 32 write-only DIRECT3 Direct access register 3 0xC 32 write-only n 0x0 0x0 CAU_DIRECT3 Direct register 3 0 32 write-only DIRECT4 Direct access register 4 0x10 32 write-only n 0x0 0x0 CAU_DIRECT4 Direct register 4 0 32 write-only DIRECT5 Direct access register 5 0x14 32 write-only n 0x0 0x0 CAU_DIRECT5 Direct register 5 0 32 write-only DIRECT6 Direct access register 6 0x18 32 write-only n 0x0 0x0 CAU_DIRECT6 Direct register 6 0 32 write-only DIRECT7 Direct access register 7 0x1C 32 write-only n 0x0 0x0 CAU_DIRECT7 Direct register 7 0 32 write-only DIRECT8 Direct access register 8 0x20 32 write-only n 0x0 0x0 CAU_DIRECT8 Direct register 8 0 32 write-only DIRECT9 Direct access register 9 0x24 32 write-only n 0x0 0x0 CAU_DIRECT9 Direct register 9 0 32 write-only LDR_CA0 General Purpose Register 0 - Load Register command 0x848 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only LDR_CA1 General Purpose Register 1 - Load Register command 0x84C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only LDR_CA2 General Purpose Register 2 - Load Register command 0x850 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only LDR_CA3 General Purpose Register 3 - Load Register command 0x854 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only LDR_CA4 General Purpose Register 4 - Load Register command 0x858 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only LDR_CA5 General Purpose Register 5 - Load Register command 0x85C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only LDR_CA6 General Purpose Register 6 - Load Register command 0x860 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only LDR_CA7 General Purpose Register 7 - Load Register command 0x864 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only LDR_CA8 General Purpose Register 8 - Load Register command 0x868 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only LDR_CAA Accumulator register - Load Register command 0x844 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only LDR_CASR Status register - Load Register command 0x840 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 RADR_CA0 General Purpose Register 0 - Reverse and Add to Register command 0x908 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only RADR_CA1 General Purpose Register 1 - Reverse and Add to Register command 0x90C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only RADR_CA2 General Purpose Register 2 - Reverse and Add to Register command 0x910 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only RADR_CA3 General Purpose Register 3 - Reverse and Add to Register command 0x914 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only RADR_CA4 General Purpose Register 4 - Reverse and Add to Register command 0x918 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only RADR_CA5 General Purpose Register 5 - Reverse and Add to Register command 0x91C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only RADR_CA6 General Purpose Register 6 - Reverse and Add to Register command 0x920 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only RADR_CA7 General Purpose Register 7 - Reverse and Add to Register command 0x924 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only RADR_CA8 General Purpose Register 8 - Reverse and Add to Register command 0x928 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only RADR_CAA Accumulator register - Reverse and Add to Register command 0x904 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only RADR_CASR Status register - Reverse and Add to Register command 0x900 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 ROTL_CA0 General Purpose Register 0 - Rotate Left command 0x9C8 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only ROTL_CA1 General Purpose Register 1 - Rotate Left command 0x9CC 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only ROTL_CA2 General Purpose Register 2 - Rotate Left command 0x9D0 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only ROTL_CA3 General Purpose Register 3 - Rotate Left command 0x9D4 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only ROTL_CA4 General Purpose Register 4 - Rotate Left command 0x9D8 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only ROTL_CA5 General Purpose Register 5 - Rotate Left command 0x9DC 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only ROTL_CA6 General Purpose Register 6 - Rotate Left command 0x9E0 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only ROTL_CA7 General Purpose Register 7 - Rotate Left command 0x9E4 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only ROTL_CA8 General Purpose Register 8 - Rotate Left command 0x9E8 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only ROTL_CAA Accumulator register - Rotate Left command 0x9C4 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only ROTL_CASR Status register - Rotate Left command 0x9C0 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 STR_CA0 General Purpose Register 0 - Store Register command 0x888 32 read-only n 0x0 0x0 CA0 CA0 0 32 read-only STR_CA1 General Purpose Register 1 - Store Register command 0x88C 32 read-only n 0x0 0x0 CA1 CA1 0 32 read-only STR_CA2 General Purpose Register 2 - Store Register command 0x890 32 read-only n 0x0 0x0 CA2 CA2 0 32 read-only STR_CA3 General Purpose Register 3 - Store Register command 0x894 32 read-only n 0x0 0x0 CA3 CA3 0 32 read-only STR_CA4 General Purpose Register 4 - Store Register command 0x898 32 read-only n 0x0 0x0 CA4 CA4 0 32 read-only STR_CA5 General Purpose Register 5 - Store Register command 0x89C 32 read-only n 0x0 0x0 CA5 CA5 0 32 read-only STR_CA6 General Purpose Register 6 - Store Register command 0x8A0 32 read-only n 0x0 0x0 CA6 CA6 0 32 read-only STR_CA7 General Purpose Register 7 - Store Register command 0x8A4 32 read-only n 0x0 0x0 CA7 CA7 0 32 read-only STR_CA8 General Purpose Register 8 - Store Register command 0x8A8 32 read-only n 0x0 0x0 CA8 CA8 0 32 read-only STR_CAA Accumulator register - Store Register command 0x884 32 read-only n 0x0 0x0 ACC ACC 0 32 read-only STR_CASR Status register - Store Register command 0x880 32 read-only n 0x0 0x0 DPE no description available 1 1 read-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 read-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 read-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 XOR_CA0 General Purpose Register 0 - Exclusive Or command 0x988 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only XOR_CA1 General Purpose Register 1 - Exclusive Or command 0x98C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only XOR_CA2 General Purpose Register 2 - Exclusive Or command 0x990 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only XOR_CA3 General Purpose Register 3 - Exclusive Or command 0x994 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only XOR_CA4 General Purpose Register 4 - Exclusive Or command 0x998 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only XOR_CA5 General Purpose Register 5 - Exclusive Or command 0x99C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only XOR_CA6 General Purpose Register 6 - Exclusive Or command 0x9A0 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only XOR_CA7 General Purpose Register 7 - Exclusive Or command 0x9A4 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only XOR_CA8 General Purpose Register 8 - Exclusive Or command 0x9A8 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only XOR_CAA Accumulator register - Exclusive Or command 0x984 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only XOR_CASR Status register - Exclusive Or command 0x980 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP 0x0 0x0 0x6 registers n CMP0 40 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 CMP1 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP 0x0 0x0 0x6 registers n CMP1 41 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 CMP2 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP 0x0 0x0 0x6 registers n CMP2 70 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 CMP3 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP 0x0 0x0 0x6 registers n CMP3 92 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 CRC Cyclic Redundancy Check CRC 0x0 0x0 0xC registers n CTRL CRC Control register 0x8 32 read-write n 0x0 0x0 FXOR Complement Read Of CRC Data Register 26 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of the CRC Data register. #1 TCRC Width of CRC protocol. 24 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 TOT Type Of Transpose For Writes 30 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOTR Type Of Transpose For Read 28 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 WAS Write CRC Data Register As Seed 25 1 read-write 0 Writes to the CRC data register are data values. #0 1 Writes to the CRC data register are seed values. #1 CTRLHU CRC_CTRLHU register. 0xB 8 read-write n 0x0 0x0 FXOR no description available 2 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of CRC data register. #1 TCRC no description available 0 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 TOT no description available 6 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOTR no description available 4 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 WAS no description available 1 1 read-write 0 Writes to CRC data register are data values. #0 1 Writes to CRC data reguster are seed values. #1 DATA CRC Data register CRC 0x0 32 read-write n 0x0 0x0 HL CRC High Lower Byte 16 8 read-write HU CRC High Upper Byte 24 8 read-write LL CRC Low Lower Byte 0 8 read-write LU CRC Low Upper Byte 8 8 read-write DATAH CRC_DATAH register. CRC 0x2 16 read-write n 0x0 0x0 DATAH DATAH stores the high 16 bits of the 16/32 bit CRC 0 16 read-write DATAHL CRC_DATAHL register. CRC 0x2 8 read-write n 0x0 0x0 DATAHL DATAHL stores the third 8 bits of the 32 bit CRC 0 8 read-write DATAHU CRC_DATAHU register. 0x3 8 read-write n 0x0 0x0 DATAHU DATAHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write DATAL CRC_DATAL register. CRC 0x0 16 read-write n 0x0 0x0 DATAL DATAL stores the lower 16 bits of the 16/32 bit CRC 0 16 read-write DATALL CRC_DATALL register. CRC 0x0 8 read-write n 0x0 0x0 DATALL CRCLL stores the first 8 bits of the 32 bit DATA 0 8 read-write DATALU CRC_DATALU register. 0x1 8 read-write n 0x0 0x0 DATALU DATALL stores the second 8 bits of the 32 bit CRC 0 8 read-write GPOLY CRC Polynomial register CRC 0x4 32 read-write n 0x0 0x0 HIGH High Polynominal Half-word 16 16 read-write LOW Low Polynominal Half-word 0 16 read-write GPOLYH CRC_GPOLYH register. CRC 0x6 16 read-write n 0x0 0x0 GPOLYH POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYHL CRC_GPOLYHL register. CRC 0x6 8 read-write n 0x0 0x0 GPOLYHL POLYHL stores the third 8 bits of the 32 bit CRC 0 8 read-write GPOLYHU CRC_GPOLYHU register. 0x7 8 read-write n 0x0 0x0 GPOLYHU POLYHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write GPOLYL CRC_GPOLYL register. CRC 0x4 16 read-write n 0x0 0x0 GPOLYL POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYLL CRC_GPOLYLL register. CRC 0x4 8 read-write n 0x0 0x0 GPOLYLL POLYLL stores the first 8 bits of the 32 bit CRC 0 8 read-write GPOLYLU CRC_GPOLYLU register. 0x5 8 read-write n 0x0 0x0 GPOLYLU POLYLL stores the second 8 bits of the 32 bit CRC 0 8 read-write DAC0 12-Bit Digital-to-Analog Converter DAC0 0x0 0x0 0x24 registers n DAC0 56 C0 DAC Control Register 0x21 8 read-write n 0x0 0x0 DACBBIEN DAC Buffer Read Pointer Bottom Flag Interrupt Enable 0 1 read-write 0 The DAC buffer read pointer bottom flag interrupt is disabled. #0 1 The DAC buffer read pointer bottom flag interrupt is enabled. #1 DACBTIEN DAC Buffer Read Pointer Top Flag Interrupt Enable 1 1 read-write 0 The DAC buffer read pointer top flag interrupt is disabled. #0 1 The DAC buffer read pointer top flag interrupt is enabled. #1 DACBWIEN DAC Buffer Watermark Interrupt Enable 2 1 read-write 0 The DAC buffer watermark interrupt is disabled. #0 1 The DAC buffer watermark interrupt is enabled. #1 DACEN DAC Enable 7 1 read-write 0 The DAC system is disabled. #0 1 The DAC system is enabled. #1 DACRFS DAC Reference Select 6 1 read-write 0 The DAC selects DACREF_1 as the reference voltage. #0 1 The DAC selects DACREF_2 as the reference voltage. #1 DACSWTRG DAC Software Trigger 4 1 write-only 0 The DAC soft trigger is not valid. #0 1 The DAC soft trigger is valid. #1 DACTRGSEL DAC Trigger Select 5 1 read-write 0 The DAC hardware trigger is selected. #0 1 The DAC software trigger is selected. #1 LPEN DAC Low Power Control 3 1 read-write 0 High-Power mode #0 1 Low-Power mode #1 C1 DAC Control Register 1 0x22 8 read-write n 0x0 0x0 DACBFEN DAC Buffer Enable 0 1 read-write 0 Buffer read pointer is disabled. The converted data is always the first word of the buffer. #0 1 Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. #1 DACBFMD DAC Buffer Work Mode Select 1 2 read-write 00 Normal mode #00 01 Swing mode #01 10 One-Time Scan mode #10 11 FIFO mode #11 DACBFWM DAC Buffer Watermark Select 3 2 read-write 00 In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining in FIFO will set watermark status bit. #00 01 In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data remaining in FIFO will set watermark status bit. #01 10 In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data remaining in FIFO will set watermark status bit. #10 11 In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data remaining in FIFO will set watermark status bit. #11 DMAEN DMA Enable Select 7 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time. #1 C2 DAC Control Register 2 0x23 8 read-write n 0x0 0x0 DACBFRP DAC Buffer Read Pointer 4 4 read-write DACBFUP DAC Buffer Upper Limit 0 4 read-write DAT0H DAC Data High Register 0x2 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT0L DAC Data Low Register 0x0 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT10H DAC Data High Register 0x7A 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT10L DAC Data Low Register 0x6E 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT11H DAC Data High Register 0x91 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT11L DAC Data Low Register 0x84 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT12H DAC Data High Register 0xAA 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT12L DAC Data Low Register 0x9C 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT13H DAC Data High Register 0xC5 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT13L DAC Data Low Register 0xB6 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT14H DAC Data High Register 0xE2 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT14L DAC Data Low Register 0xD2 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT15H DAC Data High Register 0x101 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT15L DAC Data Low Register 0xF0 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT1H DAC Data High Register 0x5 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT1L DAC Data Low Register 0x2 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT2H DAC Data High Register 0xA 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT2L DAC Data Low Register 0x6 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT3H DAC Data High Register 0x11 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT3L DAC Data Low Register 0xC 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT4H DAC Data High Register 0x1A 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT4L DAC Data Low Register 0x14 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT5H DAC Data High Register 0x25 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT5L DAC Data Low Register 0x1E 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT6H DAC Data High Register 0x32 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT6L DAC Data Low Register 0x2A 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT7H DAC Data High Register 0x41 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT7L DAC Data Low Register 0x38 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT8H DAC Data High Register 0x52 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT8L DAC Data Low Register 0x48 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT9H DAC Data High Register 0x65 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT9L DAC Data Low Register 0x5A 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write SR DAC Status Register 0x20 8 read-write n 0x0 0x0 DACBFRPBF DAC Buffer Read Pointer Bottom Position Flag 0 1 read-write 0 The DAC buffer read pointer is not equal to C2[DACBFUP]. #0 1 The DAC buffer read pointer is equal to C2[DACBFUP]. #1 DACBFRPTF DAC Buffer Read Pointer Top Position Flag 1 1 read-write 0 The DAC buffer read pointer is not zero. #0 1 The DAC buffer read pointer is zero. #1 DACBFWMF DAC Buffer Watermark Flag 2 1 read-write 0 The DAC buffer read pointer has not reached the watermark level. #0 1 The DAC buffer read pointer has reached the watermark level. #1 DMA Enhanced direct memory access controller DMA 0x0 0x0 0x1400 registers n DMA0_DMA16 0 DMA1_DMA17 1 DMA2_DMA18 2 DMA3_DMA19 3 DMA4_DMA20 4 DMA5_DMA21 5 DMA6_DMA22 6 DMA7_DMA23 7 DMA8_DMA24 8 DMA9_DMA25 9 DMA10_DMA26 10 DMA11_DMA27 11 DMA12_DMA28 12 DMA13_DMA29 13 DMA14_DMA30 14 DMA15_DMA31 15 DMA_Error 16 CDNE Clear DONE Status Bit Register 0x1C 8 write-only n 0x0 0x0 CADN Clears All DONE Bits 6 1 write-only 0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field #0 1 Clears all bits in TCDn_CSR[DONE] #1 CDNE Clear DONE Bit 0 5 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CEEI Clear Enable Error Interrupt Register 0x18 8 write-only n 0x0 0x0 CAEE Clear All Enable Error Interrupts 6 1 write-only 0 Clear only the EEI bit specified in the CEEI field #0 1 Clear all bits in EEI #1 CEEI Clear Enable Error Interrupt 0 5 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERQ Clear Enable Request Register 0x1A 8 write-only n 0x0 0x0 CAER Clear All Enable Requests 6 1 write-only 0 Clear only the ERQ bit specified in the CERQ field #0 1 Clear all bits in ERQ #1 CERQ Clear Enable Request 0 5 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERR Clear Error Register 0x1E 8 write-only n 0x0 0x0 CAEI Clear All Error Indicators 6 1 write-only 0 Clear only the ERR bit specified in the CERR field #0 1 Clear all bits in ERR #1 CERR Clear Error Indicator 0 5 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CINT Clear Interrupt Request Register 0x1F 8 write-only n 0x0 0x0 CAIR Clear All Interrupt Requests 6 1 write-only 0 Clear only the INT bit specified in the CINT field #0 1 Clear all bits in INT #1 CINT Clear Interrupt Request 0 5 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CR Control Register 0x0 32 read-write n 0x0 0x0 CLM Continuous Link Mode 6 1 read-write 0 A minor loop channel link made to itself goes through channel arbitration before being activated again. #0 1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. #1 CX Cancel Transfer 17 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. #1 ECX Error Cancel Transfer 16 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. #1 EDBG Enable Debug 1 1 read-write 0 When in debug mode, the DMA continues to operate. #0 1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. #1 EMLM Enable Minor Loop Mapping 7 1 read-write 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. #0 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. #1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write 0 Fixed priority arbitration is used for channel selection within each group. #0 1 Round robin arbitration is used for channel selection within each group. #1 ERGA Enable Round Robin Group Arbitration 3 1 read-write 0 Fixed priority arbitration is used for selection among the groups. #0 1 Round robin arbitration is used for selection among the groups. #1 GRP0PRI Channel Group 0 Priority 8 1 read-write GRP1PRI Channel Group 1 Priority 10 1 read-write HALT Halt DMA Operations 5 1 read-write 0 Normal operation #0 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. #1 HOE Halt On Error 4 1 read-write 0 Normal operation #0 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. #1 DCHPRI0 Channel n Priority Register 0x506 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI1 Channel n Priority Register 0x403 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI10 Channel n Priority Register 0xB2D 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI11 Channel n Priority Register 0xA24 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI12 Channel n Priority Register 0x1178 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI13 Channel n Priority Register 0x1069 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI14 Channel n Priority Register 0xF5B 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI15 Channel n Priority Register 0xE4E 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI16 Channel n Priority Register 0x15BE 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI17 Channel n Priority Register 0x14AB 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI18 Channel n Priority Register 0x1399 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI19 Channel n Priority Register 0x1288 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI2 Channel n Priority Register 0x301 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI20 Channel n Priority Register 0x1A14 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI21 Channel n Priority Register 0x18FD 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI22 Channel n Priority Register 0x17E7 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI23 Channel n Priority Register 0x16D2 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI24 Channel n Priority Register 0x1E7A 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI25 Channel n Priority Register 0x1D5F 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI26 Channel n Priority Register 0x1C45 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI27 Channel n Priority Register 0x1B2C 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI28 Channel n Priority Register 0x22F0 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI29 Channel n Priority Register 0x21D1 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI3 Channel n Priority Register 0x200 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI30 Channel n Priority Register 0x20B3 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI31 Channel n Priority Register 0x1F96 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI4 Channel n Priority Register 0x91C 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI5 Channel n Priority Register 0x815 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI6 Channel n Priority Register 0x70F 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI7 Channel n Priority Register 0x60A 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI8 Channel n Priority Register 0xD42 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI9 Channel n Priority Register 0xC37 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 GRPPRI Channel n Current Group Priority 4 2 read-only EARS Enable Asynchronous Request in Stop Register 0x44 32 read-write n 0x0 0x0 EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 read-write 0 Disable asynchronous DMA request for channel 0. #0 1 Enable asynchronous DMA request for channel 0. #1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 1 1 read-write 0 Disable asynchronous DMA request for channel 1 #0 1 Enable asynchronous DMA request for channel 1. #1 EDREQ_10 Enable asynchronous DMA request in stop mode for channel 10 10 1 read-write 0 Disable asynchronous DMA request for channel 10. #0 1 Enable asynchronous DMA request for channel 10. #1 EDREQ_11 Enable asynchronous DMA request in stop mode for channel 11 11 1 read-write 0 Disable asynchronous DMA request for channel 11. #0 1 Enable asynchronous DMA request for channel 11. #1 EDREQ_12 Enable asynchronous DMA request in stop mode for channel 12 12 1 read-write 0 Disable asynchronous DMA request for channel 12. #0 1 Enable asynchronous DMA request for channel 12. #1 EDREQ_13 Enable asynchronous DMA request in stop mode for channel 13 13 1 read-write 0 Disable asynchronous DMA request for channel 13. #0 1 Enable asynchronous DMA request for channel 13. #1 EDREQ_14 Enable asynchronous DMA request in stop mode for channel 14 14 1 read-write 0 Disable asynchronous DMA request for channel 14. #0 1 Enable asynchronous DMA request for channel 14. #1 EDREQ_15 Enable asynchronous DMA request in stop mode for channel 15 15 1 read-write 0 Disable asynchronous DMA request for channel 15. #0 1 Enable asynchronous DMA request for channel 15. #1 EDREQ_16 Enable asynchronous DMA request in stop mode for channel 16 16 1 read-write 0 Disable asynchronous DMA request for channel 16 #0 1 Enable asynchronous DMA request for channel 16 #1 EDREQ_17 Enable asynchronous DMA request in stop mode for channel 17 17 1 read-write 0 Disable asynchronous DMA request for channel 17 #0 1 Enable asynchronous DMA request for channel 17 #1 EDREQ_18 Enable asynchronous DMA request in stop mode for channel 18 18 1 read-write 0 Disable asynchronous DMA request for channel 18 #0 1 Enable asynchronous DMA request for channel 18 #1 EDREQ_19 Enable asynchronous DMA request in stop mode for channel 19 19 1 read-write 0 Disable asynchronous DMA request for channel 19 #0 1 Enable asynchronous DMA request for channel 19 #1 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 2 1 read-write 0 Disable asynchronous DMA request for channel 2. #0 1 Enable asynchronous DMA request for channel 2. #1 EDREQ_20 Enable asynchronous DMA request in stop mode for channel 20 20 1 read-write 0 Disable asynchronous DMA request for channel 20 #0 1 Enable asynchronous DMA request for channel 20 #1 EDREQ_21 Enable asynchronous DMA request in stop mode for channel 21 21 1 read-write 0 Disable asynchronous DMA request for channel 21 #0 1 Enable asynchronous DMA request for channel 21 #1 EDREQ_22 Enable asynchronous DMA request in stop mode for channel 22 22 1 read-write 0 Disable asynchronous DMA request for channel 22 #0 1 Enable asynchronous DMA request for channel 22 #1 EDREQ_23 Enable asynchronous DMA request in stop mode for channel 23 23 1 read-write 0 Disable asynchronous DMA request for channel 23 #0 1 Enable asynchronous DMA request for channel 23 #1 EDREQ_24 Enable asynchronous DMA request in stop mode for channel 24 24 1 read-write 0 Disable asynchronous DMA request for channel 24 #0 1 Enable asynchronous DMA request for channel 24 #1 EDREQ_25 Enable asynchronous DMA request in stop mode for channel 25 25 1 read-write 0 Disable asynchronous DMA request for channel 25 #0 1 Enable asynchronous DMA request for channel 25 #1 EDREQ_26 Enable asynchronous DMA request in stop mode for channel 26 26 1 read-write 0 Disable asynchronous DMA request for channel 26 #0 1 Enable asynchronous DMA request for channel 26 #1 EDREQ_27 Enable asynchronous DMA request in stop mode for channel 27 27 1 read-write 0 Disable asynchronous DMA request for channel 27 #0 1 Enable asynchronous DMA request for channel 27 #1 EDREQ_28 Enable asynchronous DMA request in stop mode for channel 28 28 1 read-write 0 Disable asynchronous DMA request for channel 28 #0 1 Enable asynchronous DMA request for channel 28 #1 EDREQ_29 Enable asynchronous DMA request in stop mode for channel 29 29 1 read-write 0 Disable asynchronous DMA request for channel 29 #0 1 Enable asynchronous DMA request for channel 29 #1 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 3 1 read-write 0 Disable asynchronous DMA request for channel 3. #0 1 Enable asynchronous DMA request for channel 3. #1 EDREQ_30 Enable asynchronous DMA request in stop mode for channel 30 30 1 read-write 0 Disable asynchronous DMA request for channel 30 #0 1 Enable asynchronous DMA request for channel 30 #1 EDREQ_31 Enable asynchronous DMA request in stop mode for channel 31 31 1 read-write 0 Disable asynchronous DMA request for channel 31 #0 1 Enable asynchronous DMA request for channel 31 #1 EDREQ_4 Enable asynchronous DMA request in stop mode for channel 4 4 1 read-write 0 Disable asynchronous DMA request for channel 4. #0 1 Enable asynchronous DMA request for channel 4. #1 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5 5 1 read-write 0 Disable asynchronous DMA request for channel 5. #0 1 Enable asynchronous DMA request for channel 5. #1 EDREQ_6 Enable asynchronous DMA request in stop mode for channel 6 6 1 read-write 0 Disable asynchronous DMA request for channel 6. #0 1 Enable asynchronous DMA request for channel 6. #1 EDREQ_7 Enable asynchronous DMA request in stop mode for channel 7 7 1 read-write 0 Disable asynchronous DMA request for channel 7. #0 1 Enable asynchronous DMA request for channel 7. #1 EDREQ_8 Enable asynchronous DMA request in stop mode for channel 8 8 1 read-write 0 Disable asynchronous DMA request for channel 8. #0 1 Enable asynchronous DMA request for channel 8. #1 EDREQ_9 Enable asynchronous DMA request in stop mode for channel 9 9 1 read-write 0 Disable asynchronous DMA request for channel 9. #0 1 Enable asynchronous DMA request for channel 9. #1 EEI Enable Error Interrupt Register 0x14 32 read-write n 0x0 0x0 EEI0 Enable Error Interrupt 0 0 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI1 Enable Error Interrupt 1 1 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI10 Enable Error Interrupt 10 10 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI11 Enable Error Interrupt 11 11 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI12 Enable Error Interrupt 12 12 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI13 Enable Error Interrupt 13 13 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI14 Enable Error Interrupt 14 14 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI15 Enable Error Interrupt 15 15 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI16 Enable Error Interrupt 16 16 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI17 Enable Error Interrupt 17 17 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI18 Enable Error Interrupt 18 18 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI19 Enable Error Interrupt 19 19 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI2 Enable Error Interrupt 2 2 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI20 Enable Error Interrupt 20 20 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI21 Enable Error Interrupt 21 21 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI22 Enable Error Interrupt 22 22 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI23 Enable Error Interrupt 23 23 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI24 Enable Error Interrupt 24 24 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI25 Enable Error Interrupt 25 25 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI26 Enable Error Interrupt 26 26 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI27 Enable Error Interrupt 27 27 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI28 Enable Error Interrupt 28 28 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI29 Enable Error Interrupt 29 29 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI3 Enable Error Interrupt 3 3 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI30 Enable Error Interrupt 30 30 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI31 Enable Error Interrupt 31 31 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI4 Enable Error Interrupt 4 4 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI5 Enable Error Interrupt 5 5 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI6 Enable Error Interrupt 6 6 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI7 Enable Error Interrupt 7 7 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI8 Enable Error Interrupt 8 8 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI9 Enable Error Interrupt 9 9 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 ERQ Enable Request Register 0xC 32 read-write n 0x0 0x0 ERQ0 Enable DMA Request 0 0 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ1 Enable DMA Request 1 1 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ10 Enable DMA Request 10 10 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ11 Enable DMA Request 11 11 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ12 Enable DMA Request 12 12 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ13 Enable DMA Request 13 13 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ14 Enable DMA Request 14 14 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ15 Enable DMA Request 15 15 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ16 Enable DMA Request 16 16 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ17 Enable DMA Request 17 17 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ18 Enable DMA Request 18 18 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ19 Enable DMA Request 19 19 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ2 Enable DMA Request 2 2 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ20 Enable DMA Request 20 20 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ21 Enable DMA Request 21 21 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ22 Enable DMA Request 22 22 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ23 Enable DMA Request 23 23 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ24 Enable DMA Request 24 24 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ25 Enable DMA Request 25 25 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ26 Enable DMA Request 26 26 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ27 Enable DMA Request 27 27 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ28 Enable DMA Request 28 28 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ29 Enable DMA Request 29 29 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ3 Enable DMA Request 3 3 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ30 Enable DMA Request 30 30 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ31 Enable DMA Request 31 31 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ4 Enable DMA Request 4 4 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ5 Enable DMA Request 5 5 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ6 Enable DMA Request 6 6 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ7 Enable DMA Request 7 7 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ8 Enable DMA Request 8 8 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ9 Enable DMA Request 9 9 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERR Error Register 0x2C 32 read-write n 0x0 0x0 ERR0 Error In Channel 0 0 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR1 Error In Channel 1 1 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR10 Error In Channel 10 10 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR11 Error In Channel 11 11 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR12 Error In Channel 12 12 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR13 Error In Channel 13 13 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR14 Error In Channel 14 14 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR15 Error In Channel 15 15 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR16 Error In Channel 16 16 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR17 Error In Channel 17 17 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR18 Error In Channel 18 18 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR19 Error In Channel 19 19 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR2 Error In Channel 2 2 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR20 Error In Channel 20 20 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR21 Error In Channel 21 21 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR22 Error In Channel 22 22 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR23 Error In Channel 23 23 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR24 Error In Channel 24 24 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR25 Error In Channel 25 25 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR26 Error In Channel 26 26 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR27 Error In Channel 27 27 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR28 Error In Channel 28 28 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR29 Error In Channel 29 29 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR3 Error In Channel 3 3 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR30 Error In Channel 30 30 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR31 Error In Channel 31 31 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR4 Error In Channel 4 4 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR5 Error In Channel 5 5 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR6 Error In Channel 6 6 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR7 Error In Channel 7 7 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR8 Error In Channel 8 8 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR9 Error In Channel 9 9 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ES Error Status Register 0x4 32 read-only n 0x0 0x0 CPE Channel Priority Error 14 1 read-only 0 No channel priority error #0 1 The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique. #1 DAE Destination Address Error 5 1 read-only 0 No destination address configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. #1 DBE Destination Bus Error 0 1 read-only 0 No destination bus error #0 1 The last recorded error was a bus error on a destination write #1 DOE Destination Offset Error 4 1 read-only 0 No destination offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. #1 ECX Transfer Canceled 16 1 read-only 0 No canceled transfers #0 1 The last recorded entry was a canceled transfer by the error cancel transfer input #1 ERRCHN Error Channel Number or Canceled Channel Number 8 5 read-only GPE Group Priority Error 15 1 read-only 0 No group priority error #0 1 The last recorded error was a configuration error among the group priorities. All group priorities are not unique. #1 NCE NBYTES/CITER Configuration Error 3 1 read-only 0 No NBYTES/CITER configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] #1 SAE Source Address Error 7 1 read-only 0 No source address configuration error. #0 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. #1 SBE Source Bus Error 1 1 read-only 0 No source bus error #0 1 The last recorded error was a bus error on a source read #1 SGE Scatter/Gather Configuration Error 2 1 read-only 0 No scatter/gather configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. #1 SOE Source Offset Error 6 1 read-only 0 No source offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. #1 VLD Logical OR of all ERR status bits 31 1 read-only 0 No ERR bits are set. #0 1 At least one ERR bit is set indicating a valid error exists that has not been cleared. #1 HRS Hardware Request Status Register 0x34 32 read-only n 0x0 0x0 HRS0 Hardware Request Status Channel 0 0 1 read-only 0 A hardware service request for channel 0 is not present #0 1 A hardware service request for channel 0 is present #1 HRS1 Hardware Request Status Channel 1 1 1 read-only 0 A hardware service request for channel 1 is not present #0 1 A hardware service request for channel 1 is present #1 HRS10 Hardware Request Status Channel 10 10 1 read-only 0 A hardware service request for channel 10 is not present #0 1 A hardware service request for channel 10 is present #1 HRS11 Hardware Request Status Channel 11 11 1 read-only 0 A hardware service request for channel 11 is not present #0 1 A hardware service request for channel 11 is present #1 HRS12 Hardware Request Status Channel 12 12 1 read-only 0 A hardware service request for channel 12 is not present #0 1 A hardware service request for channel 12 is present #1 HRS13 Hardware Request Status Channel 13 13 1 read-only 0 A hardware service request for channel 13 is not present #0 1 A hardware service request for channel 13 is present #1 HRS14 Hardware Request Status Channel 14 14 1 read-only 0 A hardware service request for channel 14 is not present #0 1 A hardware service request for channel 14 is present #1 HRS15 Hardware Request Status Channel 15 15 1 read-only 0 A hardware service request for channel 15 is not present #0 1 A hardware service request for channel 15 is present #1 HRS16 Hardware Request Status Channel 16 16 1 read-only 0 A hardware service request for channel 16 is not present #0 1 A hardware service request for channel 16 is present #1 HRS17 Hardware Request Status Channel 17 17 1 read-only 0 A hardware service request for channel 17 is not present #0 1 A hardware service request for channel 17 is present #1 HRS18 Hardware Request Status Channel 18 18 1 read-only 0 A hardware service request for channel 18 is not present #0 1 A hardware service request for channel 18 is present #1 HRS19 Hardware Request Status Channel 19 19 1 read-only 0 A hardware service request for channel 19 is not present #0 1 A hardware service request for channel 19 is present #1 HRS2 Hardware Request Status Channel 2 2 1 read-only 0 A hardware service request for channel 2 is not present #0 1 A hardware service request for channel 2 is present #1 HRS20 Hardware Request Status Channel 20 20 1 read-only 0 A hardware service request for channel 20 is not present #0 1 A hardware service request for channel 20 is present #1 HRS21 Hardware Request Status Channel 21 21 1 read-only 0 A hardware service request for channel 21 is not present #0 1 A hardware service request for channel 21 is present #1 HRS22 Hardware Request Status Channel 22 22 1 read-only 0 A hardware service request for channel 22 is not present #0 1 A hardware service request for channel 22 is present #1 HRS23 Hardware Request Status Channel 23 23 1 read-only 0 A hardware service request for channel 23 is not present #0 1 A hardware service request for channel 23 is present #1 HRS24 Hardware Request Status Channel 24 24 1 read-only 0 A hardware service request for channel 24 is not present #0 1 A hardware service request for channel 24 is present #1 HRS25 Hardware Request Status Channel 25 25 1 read-only 0 A hardware service request for channel 25 is not present #0 1 A hardware service request for channel 25 is present #1 HRS26 Hardware Request Status Channel 26 26 1 read-only 0 A hardware service request for channel 26 is not present #0 1 A hardware service request for channel 26 is present #1 HRS27 Hardware Request Status Channel 27 27 1 read-only 0 A hardware service request for channel 27 is not present #0 1 A hardware service request for channel 27 is present #1 HRS28 Hardware Request Status Channel 28 28 1 read-only 0 A hardware service request for channel 28 is not present #0 1 A hardware service request for channel 28 is present #1 HRS29 Hardware Request Status Channel 29 29 1 read-only 0 A hardware service request for channel 29 is not preset #0 1 A hardware service request for channel 29 is present #1 HRS3 Hardware Request Status Channel 3 3 1 read-only 0 A hardware service request for channel 3 is not present #0 1 A hardware service request for channel 3 is present #1 HRS30 Hardware Request Status Channel 30 30 1 read-only 0 A hardware service request for channel 30 is not present #0 1 A hardware service request for for channel 30 is present #1 HRS31 Hardware Request Status Channel 31 31 1 read-only 0 A hardware service request for channel 31 is not present #0 1 A hardware service request for channel 31 is present #1 HRS4 Hardware Request Status Channel 4 4 1 read-only 0 A hardware service request for channel 4 is not present #0 1 A hardware service request for channel 4 is present #1 HRS5 Hardware Request Status Channel 5 5 1 read-only 0 A hardware service request for channel 5 is not present #0 1 A hardware service request for channel 5 is present #1 HRS6 Hardware Request Status Channel 6 6 1 read-only 0 A hardware service request for channel 6 is not present #0 1 A hardware service request for channel 6 is present #1 HRS7 Hardware Request Status Channel 7 7 1 read-only 0 A hardware service request for channel 7 is not present #0 1 A hardware service request for channel 7 is present #1 HRS8 Hardware Request Status Channel 8 8 1 read-only 0 A hardware service request for channel 8 is not present #0 1 A hardware service request for channel 8 is present #1 HRS9 Hardware Request Status Channel 9 9 1 read-only 0 A hardware service request for channel 9 is not present #0 1 A hardware service request for channel 9 is present #1 INT Interrupt Request Register 0x24 32 read-write n 0x0 0x0 INT0 Interrupt Request 0 0 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT1 Interrupt Request 1 1 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT10 Interrupt Request 10 10 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT11 Interrupt Request 11 11 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT12 Interrupt Request 12 12 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT13 Interrupt Request 13 13 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT14 Interrupt Request 14 14 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT15 Interrupt Request 15 15 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT16 Interrupt Request 16 16 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT17 Interrupt Request 17 17 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT18 Interrupt Request 18 18 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT19 Interrupt Request 19 19 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT2 Interrupt Request 2 2 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT20 Interrupt Request 20 20 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT21 Interrupt Request 21 21 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT22 Interrupt Request 22 22 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT23 Interrupt Request 23 23 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT24 Interrupt Request 24 24 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT25 Interrupt Request 25 25 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT26 Interrupt Request 26 26 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT27 Interrupt Request 27 27 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT28 Interrupt Request 28 28 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT29 Interrupt Request 29 29 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT3 Interrupt Request 3 3 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT30 Interrupt Request 30 30 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT31 Interrupt Request 31 31 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT4 Interrupt Request 4 4 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT5 Interrupt Request 5 5 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT6 Interrupt Request 6 6 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT7 Interrupt Request 7 7 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT8 Interrupt Request 8 8 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT9 Interrupt Request 9 9 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 SEEI Set Enable Error Interrupt Register 0x19 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAEE Sets All Enable Error Interrupts 6 1 write-only 0 Set only the EEI bit specified in the SEEI field. #0 1 Sets all bits in EEI #1 SEEI Set Enable Error Interrupt 0 5 write-only SERQ Set Enable Request Register 0x1B 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAER Set All Enable Requests 6 1 write-only 0 Set only the ERQ bit specified in the SERQ field #0 1 Set all bits in ERQ #1 SERQ Set Enable Request 0 5 write-only SSRT Set START Bit Register 0x1D 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAST Set All START Bits (activates all channels) 6 1 write-only 0 Set only the TCDn_CSR[START] bit specified in the SSRT field #0 1 Set all bits in TCDn_CSR[START] #1 SSRT Set START Bit 0 5 write-only TCD0_ATTR TCD Transfer Attributes 0x200C 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD0_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x203C 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x203C 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD0_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x202C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x202C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD0_CSR TCD Control and Status 0x2038 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD0_DADDR TCD Destination Address 0x2020 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD0_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x2030 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD0_DOFF TCD Signed Destination Address Offset 0x2028 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD0_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x2010 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD0_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x2010 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x2010 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_SADDR TCD Source Address 0x2000 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD0_SLAST TCD Last Source Address Adjustment 0x2018 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD0_SOFF TCD Signed Source Address Offset 0x2008 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD10_ATTR TCD Transfer Attributes 0xC728 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD10_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xC848 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD10_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xC848 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD10_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xC7E8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD10_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xC7E8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD10_CSR TCD Control and Status 0xC830 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD10_DADDR TCD Destination Address 0xC7A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD10_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xC800 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD10_DOFF TCD Signed Destination Address Offset 0xC7D0 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD10_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0xC740 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD10_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0xC740 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD10_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0xC740 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD10_SADDR TCD Source Address 0xC6E0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD10_SLAST TCD Last Source Address Adjustment 0xC770 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD10_SOFF TCD Signed Source Address Offset 0xC710 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD11_ATTR TCD Transfer Attributes 0xD88E 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD11_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xD9C6 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD11_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xD9C6 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD11_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xD95E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD11_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xD95E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD11_CSR TCD Control and Status 0xD9AC 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD11_DADDR TCD Destination Address 0xD910 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD11_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xD978 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD11_DOFF TCD Signed Destination Address Offset 0xD944 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD11_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0xD8A8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD11_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0xD8A8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD11_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0xD8A8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD11_SADDR TCD Source Address 0xD840 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD11_SLAST TCD Last Source Address Adjustment 0xD8DC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD11_SOFF TCD Signed Source Address Offset 0xD874 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD12_ATTR TCD Transfer Attributes 0xEA14 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD12_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xEB64 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD12_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xEB64 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD12_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xEAF4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD12_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xEAF4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD12_CSR TCD Control and Status 0xEB48 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD12_DADDR TCD Destination Address 0xEAA0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD12_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xEB10 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD12_DOFF TCD Signed Destination Address Offset 0xEAD8 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD12_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0xEA30 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD12_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0xEA30 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD12_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0xEA30 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD12_SADDR TCD Source Address 0xE9C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD12_SLAST TCD Last Source Address Adjustment 0xEA68 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD12_SOFF TCD Signed Source Address Offset 0xE9F8 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD13_ATTR TCD Transfer Attributes 0xFBBA 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD13_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xFD22 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD13_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xFD22 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD13_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xFCAA 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD13_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xFCAA 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD13_CSR TCD Control and Status 0xFD04 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD13_DADDR TCD Destination Address 0xFC50 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD13_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xFCC8 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD13_DOFF TCD Signed Destination Address Offset 0xFC8C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD13_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0xFBD8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD13_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0xFBD8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD13_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0xFBD8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD13_SADDR TCD Source Address 0xFB60 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD13_SLAST TCD Last Source Address Adjustment 0xFC14 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD13_SOFF TCD Signed Source Address Offset 0xFB9C 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD14_ATTR TCD Transfer Attributes 0x10D80 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD14_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x10F00 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD14_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x10F00 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD14_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x10E80 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD14_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x10E80 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD14_CSR TCD Control and Status 0x10EE0 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD14_DADDR TCD Destination Address 0x10E20 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD14_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10EA0 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD14_DOFF TCD Signed Destination Address Offset 0x10E60 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD14_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x10DA0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD14_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x10DA0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD14_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x10DA0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD14_SADDR TCD Source Address 0x10D20 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD14_SLAST TCD Last Source Address Adjustment 0x10DE0 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD14_SOFF TCD Signed Source Address Offset 0x10D60 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD15_ATTR TCD Transfer Attributes 0x11F66 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD15_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x120FE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD15_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x120FE 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD15_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x12076 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD15_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x12076 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD15_CSR TCD Control and Status 0x120DC 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD15_DADDR TCD Destination Address 0x12010 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD15_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x12098 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD15_DOFF TCD Signed Destination Address Offset 0x12054 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD15_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x11F88 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD15_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x11F88 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD15_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x11F88 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD15_SADDR TCD Source Address 0x11F00 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD15_SLAST TCD Last Source Address Adjustment 0x11FCC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD15_SOFF TCD Signed Source Address Offset 0x11F44 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD16_ATTR TCD Transfer Attributes 0x1316C 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD16_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1331C 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD16_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1331C 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD16_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1328C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD16_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1328C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD16_CSR TCD Control and Status 0x132F8 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD16_DADDR TCD Destination Address 0x13220 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD16_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x132B0 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD16_DOFF TCD Signed Destination Address Offset 0x13268 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD16_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x13190 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD16_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x13190 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD16_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x13190 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD16_SADDR TCD Source Address 0x13100 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD16_SLAST TCD Last Source Address Adjustment 0x131D8 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD16_SOFF TCD Signed Source Address Offset 0x13148 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD17_ATTR TCD Transfer Attributes 0x14392 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD17_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1455A 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD17_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1455A 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD17_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x144C2 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD17_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x144C2 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD17_CSR TCD Control and Status 0x14534 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD17_DADDR TCD Destination Address 0x14450 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD17_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x144E8 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD17_DOFF TCD Signed Destination Address Offset 0x1449C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD17_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x143B8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD17_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x143B8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD17_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x143B8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD17_SADDR TCD Source Address 0x14320 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD17_SLAST TCD Last Source Address Adjustment 0x14404 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD17_SOFF TCD Signed Source Address Offset 0x1436C 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD18_ATTR TCD Transfer Attributes 0x155D8 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD18_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x157B8 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD18_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x157B8 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD18_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x15718 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD18_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x15718 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD18_CSR TCD Control and Status 0x15790 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD18_DADDR TCD Destination Address 0x156A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD18_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x15740 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD18_DOFF TCD Signed Destination Address Offset 0x156F0 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD18_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x15600 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD18_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x15600 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD18_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x15600 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD18_SADDR TCD Source Address 0x15560 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD18_SLAST TCD Last Source Address Adjustment 0x15650 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD18_SOFF TCD Signed Source Address Offset 0x155B0 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD19_ATTR TCD Transfer Attributes 0x1683E 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD19_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x16A36 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD19_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x16A36 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD19_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1698E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD19_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1698E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD19_CSR TCD Control and Status 0x16A0C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD19_DADDR TCD Destination Address 0x16910 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD19_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x169B8 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD19_DOFF TCD Signed Destination Address Offset 0x16964 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD19_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x16868 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD19_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x16868 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD19_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x16868 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD19_SADDR TCD Source Address 0x167C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD19_SLAST TCD Last Source Address Adjustment 0x168BC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD19_SOFF TCD Signed Source Address Offset 0x16814 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD1_ATTR TCD Transfer Attributes 0x3032 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD1_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x307A 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x307A 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD1_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x3062 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x3062 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD1_CSR TCD Control and Status 0x3074 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD1_DADDR TCD Destination Address 0x3050 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD1_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x3068 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD1_DOFF TCD Signed Destination Address Offset 0x305C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD1_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x3038 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD1_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x3038 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x3038 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_SADDR TCD Source Address 0x3020 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD1_SLAST TCD Last Source Address Adjustment 0x3044 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD1_SOFF TCD Signed Source Address Offset 0x302C 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD20_ATTR TCD Transfer Attributes 0x17AC4 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD20_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x17CD4 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD20_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x17CD4 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD20_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x17C24 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD20_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x17C24 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD20_CSR TCD Control and Status 0x17CA8 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD20_DADDR TCD Destination Address 0x17BA0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD20_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x17C50 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD20_DOFF TCD Signed Destination Address Offset 0x17BF8 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD20_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x17AF0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD20_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x17AF0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD20_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x17AF0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD20_SADDR TCD Source Address 0x17A40 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD20_SLAST TCD Last Source Address Adjustment 0x17B48 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD20_SOFF TCD Signed Source Address Offset 0x17A98 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD21_ATTR TCD Transfer Attributes 0x18D6A 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD21_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x18F92 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD21_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x18F92 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD21_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x18EDA 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD21_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x18EDA 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD21_CSR TCD Control and Status 0x18F64 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD21_DADDR TCD Destination Address 0x18E50 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD21_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x18F08 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD21_DOFF TCD Signed Destination Address Offset 0x18EAC 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD21_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x18D98 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD21_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x18D98 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD21_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x18D98 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD21_SADDR TCD Source Address 0x18CE0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD21_SLAST TCD Last Source Address Adjustment 0x18DF4 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD21_SOFF TCD Signed Source Address Offset 0x18D3C 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD22_ATTR TCD Transfer Attributes 0x1A030 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD22_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1A270 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD22_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1A270 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD22_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1A1B0 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD22_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1A1B0 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD22_CSR TCD Control and Status 0x1A240 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD22_DADDR TCD Destination Address 0x1A120 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD22_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1A1E0 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD22_DOFF TCD Signed Destination Address Offset 0x1A180 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD22_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x1A060 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD22_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x1A060 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD22_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x1A060 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD22_SADDR TCD Source Address 0x19FA0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD22_SLAST TCD Last Source Address Adjustment 0x1A0C0 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD22_SOFF TCD Signed Source Address Offset 0x1A000 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD23_ATTR TCD Transfer Attributes 0x1B316 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD23_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1B56E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD23_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1B56E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD23_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1B4A6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD23_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1B4A6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD23_CSR TCD Control and Status 0x1B53C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD23_DADDR TCD Destination Address 0x1B410 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD23_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1B4D8 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD23_DOFF TCD Signed Destination Address Offset 0x1B474 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD23_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x1B348 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD23_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x1B348 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD23_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x1B348 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD23_SADDR TCD Source Address 0x1B280 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD23_SLAST TCD Last Source Address Adjustment 0x1B3AC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD23_SOFF TCD Signed Source Address Offset 0x1B2E4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD24_ATTR TCD Transfer Attributes 0x1C61C 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD24_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1C88C 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD24_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1C88C 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD24_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1C7BC 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD24_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1C7BC 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD24_CSR TCD Control and Status 0x1C858 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD24_DADDR TCD Destination Address 0x1C720 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD24_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1C7F0 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD24_DOFF TCD Signed Destination Address Offset 0x1C788 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD24_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x1C650 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD24_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x1C650 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD24_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x1C650 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD24_SADDR TCD Source Address 0x1C580 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD24_SLAST TCD Last Source Address Adjustment 0x1C6B8 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD24_SOFF TCD Signed Source Address Offset 0x1C5E8 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD25_ATTR TCD Transfer Attributes 0x1D942 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD25_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1DBCA 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD25_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1DBCA 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD25_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1DAF2 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD25_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1DAF2 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD25_CSR TCD Control and Status 0x1DB94 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD25_DADDR TCD Destination Address 0x1DA50 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD25_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1DB28 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD25_DOFF TCD Signed Destination Address Offset 0x1DABC 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD25_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x1D978 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD25_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x1D978 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD25_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x1D978 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD25_SADDR TCD Source Address 0x1D8A0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD25_SLAST TCD Last Source Address Adjustment 0x1D9E4 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD25_SOFF TCD Signed Source Address Offset 0x1D90C 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD26_ATTR TCD Transfer Attributes 0x1EC88 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD26_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1EF28 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD26_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1EF28 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD26_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1EE48 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD26_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1EE48 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD26_CSR TCD Control and Status 0x1EEF0 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD26_DADDR TCD Destination Address 0x1EDA0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD26_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1EE80 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD26_DOFF TCD Signed Destination Address Offset 0x1EE10 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD26_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x1ECC0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD26_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x1ECC0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD26_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x1ECC0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD26_SADDR TCD Source Address 0x1EBE0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD26_SLAST TCD Last Source Address Adjustment 0x1ED30 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD26_SOFF TCD Signed Source Address Offset 0x1EC50 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD27_ATTR TCD Transfer Attributes 0x1FFEE 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD27_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x202A6 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD27_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x202A6 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD27_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x201BE 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD27_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x201BE 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD27_CSR TCD Control and Status 0x2026C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD27_DADDR TCD Destination Address 0x20110 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD27_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x201F8 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD27_DOFF TCD Signed Destination Address Offset 0x20184 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD27_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x20028 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD27_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x20028 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD27_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x20028 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD27_SADDR TCD Source Address 0x1FF40 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD27_SLAST TCD Last Source Address Adjustment 0x2009C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD27_SOFF TCD Signed Source Address Offset 0x1FFB4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD28_ATTR TCD Transfer Attributes 0x21374 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD28_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x21644 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD28_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x21644 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD28_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x21554 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD28_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x21554 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD28_CSR TCD Control and Status 0x21608 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD28_DADDR TCD Destination Address 0x214A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD28_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x21590 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD28_DOFF TCD Signed Destination Address Offset 0x21518 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD28_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x213B0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD28_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x213B0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD28_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x213B0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD28_SADDR TCD Source Address 0x212C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD28_SLAST TCD Last Source Address Adjustment 0x21428 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD28_SOFF TCD Signed Source Address Offset 0x21338 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD29_ATTR TCD Transfer Attributes 0x2271A 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD29_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x22A02 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD29_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x22A02 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD29_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x2290A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD29_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x2290A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD29_CSR TCD Control and Status 0x229C4 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD29_DADDR TCD Destination Address 0x22850 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD29_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x22948 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD29_DOFF TCD Signed Destination Address Offset 0x228CC 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD29_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x22758 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD29_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x22758 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD29_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x22758 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD29_SADDR TCD Source Address 0x22660 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD29_SLAST TCD Last Source Address Adjustment 0x227D4 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD29_SOFF TCD Signed Source Address Offset 0x226DC 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD2_ATTR TCD Transfer Attributes 0x4078 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD2_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x40D8 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x40D8 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD2_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x40B8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x40B8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD2_CSR TCD Control and Status 0x40D0 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD2_DADDR TCD Destination Address 0x40A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD2_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x40C0 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD2_DOFF TCD Signed Destination Address Offset 0x40B0 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD2_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x4080 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD2_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x4080 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x4080 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_SADDR TCD Source Address 0x4060 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD2_SLAST TCD Last Source Address Adjustment 0x4090 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD2_SOFF TCD Signed Source Address Offset 0x4070 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD30_ATTR TCD Transfer Attributes 0x23AE0 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD30_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x23DE0 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD30_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x23DE0 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD30_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x23CE0 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD30_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x23CE0 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD30_CSR TCD Control and Status 0x23DA0 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD30_DADDR TCD Destination Address 0x23C20 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD30_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x23D20 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD30_DOFF TCD Signed Destination Address Offset 0x23CA0 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD30_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x23B20 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD30_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x23B20 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD30_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x23B20 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD30_SADDR TCD Source Address 0x23A20 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD30_SLAST TCD Last Source Address Adjustment 0x23BA0 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD30_SOFF TCD Signed Source Address Offset 0x23AA0 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD31_ATTR TCD Transfer Attributes 0x24EC6 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD31_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x251DE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD31_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x251DE 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD31_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x250D6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD31_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x250D6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD31_CSR TCD Control and Status 0x2519C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD31_DADDR TCD Destination Address 0x25010 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD31_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x25118 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD31_DOFF TCD Signed Destination Address Offset 0x25094 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD31_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x24F08 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD31_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x24F08 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD31_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x24F08 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD31_SADDR TCD Source Address 0x24E00 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD31_SLAST TCD Last Source Address Adjustment 0x24F8C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD31_SOFF TCD Signed Source Address Offset 0x24E84 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD3_ATTR TCD Transfer Attributes 0x50DE 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD3_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x5156 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x5156 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD3_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x512E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x512E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD3_CSR TCD Control and Status 0x514C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD3_DADDR TCD Destination Address 0x5110 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD3_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x5138 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD3_DOFF TCD Signed Destination Address Offset 0x5124 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD3_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x50E8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD3_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x50E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x50E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_SADDR TCD Source Address 0x50C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD3_SLAST TCD Last Source Address Adjustment 0x50FC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD3_SOFF TCD Signed Source Address Offset 0x50D4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD4_ATTR TCD Transfer Attributes 0x6164 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD4_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x61F4 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD4_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x61F4 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD4_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x61C4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD4_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x61C4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD4_CSR TCD Control and Status 0x61E8 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD4_DADDR TCD Destination Address 0x61A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD4_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x61D0 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD4_DOFF TCD Signed Destination Address Offset 0x61B8 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD4_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x6170 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD4_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x6170 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD4_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x6170 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD4_SADDR TCD Source Address 0x6140 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD4_SLAST TCD Last Source Address Adjustment 0x6188 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD4_SOFF TCD Signed Source Address Offset 0x6158 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD5_ATTR TCD Transfer Attributes 0x720A 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD5_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x72B2 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD5_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x72B2 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD5_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x727A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD5_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x727A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD5_CSR TCD Control and Status 0x72A4 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD5_DADDR TCD Destination Address 0x7250 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD5_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x7288 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD5_DOFF TCD Signed Destination Address Offset 0x726C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD5_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x7218 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD5_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x7218 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD5_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x7218 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD5_SADDR TCD Source Address 0x71E0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD5_SLAST TCD Last Source Address Adjustment 0x7234 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD5_SOFF TCD Signed Source Address Offset 0x71FC 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD6_ATTR TCD Transfer Attributes 0x82D0 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD6_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x8390 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD6_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x8390 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD6_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x8350 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD6_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x8350 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD6_CSR TCD Control and Status 0x8380 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD6_DADDR TCD Destination Address 0x8320 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD6_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x8360 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD6_DOFF TCD Signed Destination Address Offset 0x8340 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD6_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x82E0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD6_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x82E0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD6_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x82E0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD6_SADDR TCD Source Address 0x82A0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD6_SLAST TCD Last Source Address Adjustment 0x8300 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD6_SOFF TCD Signed Source Address Offset 0x82C0 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD7_ATTR TCD Transfer Attributes 0x93B6 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD7_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x948E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD7_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x948E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD7_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x9446 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD7_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x9446 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD7_CSR TCD Control and Status 0x947C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD7_DADDR TCD Destination Address 0x9410 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD7_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x9458 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD7_DOFF TCD Signed Destination Address Offset 0x9434 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD7_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0x93C8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD7_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0x93C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD7_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0x93C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD7_SADDR TCD Source Address 0x9380 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD7_SLAST TCD Last Source Address Adjustment 0x93EC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD7_SOFF TCD Signed Source Address Offset 0x93A4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD8_ATTR TCD Transfer Attributes 0xA4BC 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD8_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xA5AC 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD8_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xA5AC 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD8_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xA55C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD8_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xA55C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD8_CSR TCD Control and Status 0xA598 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD8_DADDR TCD Destination Address 0xA520 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD8_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xA570 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD8_DOFF TCD Signed Destination Address Offset 0xA548 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD8_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0xA4D0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD8_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0xA4D0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD8_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0xA4D0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD8_SADDR TCD Source Address 0xA480 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD8_SLAST TCD Last Source Address Adjustment 0xA4F8 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD8_SOFF TCD Signed Source Address Offset 0xA4A8 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD9_ATTR TCD Transfer Attributes 0xB5E2 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte burst #100 101 32-byte burst #101 TCD9_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xB6EA 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD9_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xB6EA 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write TCD9_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xB692 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD9_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xB692 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 5 read-write TCD9_CSR TCD Control and Status 0xB6D4 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 5 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD9_DADDR TCD Destination Address 0xB650 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD9_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xB6A8 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD9_DOFF TCD Signed Destination Address Offset 0xB67C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD9_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA 0xB5F8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD9_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA 0xB5F8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD9_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA 0xB5F8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD9_SADDR TCD Source Address 0xB5A0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD9_SLAST TCD Last Source Address Adjustment 0xB624 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD9_SOFF TCD Signed Source Address Offset 0xB5CC 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write DMAMUX DMA channel multiplexor DMAMUX 0x0 0x0 0x20 registers n CHCFG0 Channel Configuration register 0x0 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG1 Channel Configuration register 0x1 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG10 Channel Configuration register 0x37 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG11 Channel Configuration register 0x42 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG12 Channel Configuration register 0x4E 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG13 Channel Configuration register 0x5B 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG14 Channel Configuration register 0x69 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG15 Channel Configuration register 0x78 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG16 Channel Configuration register 0x88 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG17 Channel Configuration register 0x99 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG18 Channel Configuration register 0xAB 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG19 Channel Configuration register 0xBE 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG2 Channel Configuration register 0x3 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG20 Channel Configuration register 0xD2 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG21 Channel Configuration register 0xE7 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG22 Channel Configuration register 0xFD 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG23 Channel Configuration register 0x114 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG24 Channel Configuration register 0x12C 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG25 Channel Configuration register 0x145 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG26 Channel Configuration register 0x15F 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG27 Channel Configuration register 0x17A 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG28 Channel Configuration register 0x196 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG29 Channel Configuration register 0x1B3 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG3 Channel Configuration register 0x6 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG30 Channel Configuration register 0x1D1 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG31 Channel Configuration register 0x1F0 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG4 Channel Configuration register 0xA 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG5 Channel Configuration register 0xF 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG6 Channel Configuration register 0x15 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG7 Channel Configuration register 0x1C 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG8 Channel Configuration register 0x24 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG9 Channel Configuration register 0x2D 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write 0 Disable_Signal #0 2 UART0_Rx_Signal #10 4 UART1_Rx_Signal #100 8 PWM0_WR2_Signal #1000 16 SPI0_Rx_Signal #10000 32 FTM1_Channel0_Signal #100000 33 FTM1_Channel1_Signal #100001 17 SPI0_Tx_Signal #10001 34 CMP3_Signal #100010 9 PWM0_WR3_Signal #1001 18 XBARA_OUT_0_Signal #10010 36 FTM3_Channel0_Signal #100100 37 FTM3_Channel1_Signal #100101 19 XBARA_OUT_1_Signal #10011 38 FTM3_Channel2_Signal #100110 39 FTM3_Channel3_Signal #100111 5 UART1_Tx_Signal #101 10 PWM0_CP0_Signal #1010 20 XBARA_OUT_2_Signal #10100 40 HSADC0A_Signal #101000 41 HSADC0B_Signal #101001 21 XBARA_OUT_3_Signal #10101 42 CMP0_Signal #101010 43 CMP1_Signal #101011 11 PWM0_CP1_Signal #1011 22 I2C0_Signal #10110 44 CMP2_Signal #101100 45 DAC0_Signal #101101 47 PDB1_Signal #101111 3 UART0_Tx_Signal #11 6 PWM0_WR0_Signal #110 12 PWM0_CP2_Signal #1100 24 FTM0_Channel0_Signal #11000 48 PDB0_Signal #110000 49 PortA_Signal #110001 25 FTM0_Channel1_Signal #11001 50 PortB_Signal #110010 51 PortC_Signal #110011 13 PWM0_CP3_Signal #1101 26 FTM0_Channel2_Signal #11010 52 PortD_Signal #110100 53 PortE_Signal #110101 27 FTM0_Channel3_Signal #11011 54 FTM3_Channel4_Signal #110110 55 FTM3_Channel5_Signal #110111 7 PWM0_WR1_Signal #111 14 CAN0_Signal #1110 28 FTM0_Channel4_Signal #11100 56 FTM3_Channel6_Signal #111000 57 FTM3_Channel7_Signal #111001 29 FTM0_Channel5_Signal #11101 15 CAN1_Signal #1111 30 FTM0_Channel6_Signal #11110 60 AlwaysOn60_Signal #111100 61 AlwaysOn61_Signal #111101 31 FTM0_Channel7_Signal #11111 62 AlwaysOn62_Signal #111110 63 AlwaysOn63_Signal #111111 TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 ENC Quadrature Decoder ENC 0x0 0x0 0x28 registers n ENC_COMPARE 66 ENC_HOME 67 ENC_WDOG_SAB 68 ENC_INDEX 69 CTRL Control Register 0x0 16 read-write n 0x0 0x0 CMPIE Compare Interrupt Enable 0 1 read-write 0 Compare interrupt is disabled #0 1 Compare interrupt is enabled #1 CMPIRQ Compare Interrupt Request 1 1 read-write 0 No match has occurred #0 1 COMP match has occurred #1 DIE Watchdog Timeout Interrupt Enable 3 1 read-write 0 Watchdog timer interrupt is disabled #0 1 Watchdog timer interrupt is enabled #1 DIRQ Watchdog Timeout Interrupt Request 4 1 read-write 0 No interrupt has occurred #0 1 Watchdog timeout interrupt has occurred #1 HIE HOME Interrupt Enable 14 1 read-write 0 Disable HOME interrupts #0 1 Enable HOME interrupts #1 HIP Enable HOME to Initialize Position Counters UPOS and LPOS 13 1 read-write 0 No action #0 1 HOME signal initializes the position counter #1 HIRQ HOME Signal Transition Interrupt Request 15 1 read-write 0 No interrupt #0 1 HOME signal transition interrupt request #1 HNE Use Negative Edge of HOME Input 12 1 read-write 0 Use positive going edge-to-trigger initialization of position counters UPOS and LPOS #0 1 Use negative going edge-to-trigger initialization of position counters UPOS and LPOS #1 PH1 Enable Signal Phase Count Mode 9 1 read-write 0 Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal. #0 1 Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, PHASEB = 1, then count up #1 REV Enable Reverse Direction Counting 10 1 read-write 0 Count normally #0 1 Count in the reverse direction #1 SWIP Software Triggered Initialization of Position Counters UPOS and LPOS 11 1 write-only 0 No action #0 1 Initialize position counter #1 WDE Watchdog Enable 2 1 read-write 0 Watchdog timer is disabled #0 1 Watchdog timer is enabled #1 XIE INDEX Pulse Interrupt Enable 7 1 read-write 0 INDEX pulse interrupt is disabled #0 1 INDEX pulse interrupt is enabled #1 XIP INDEX Triggered Initialization of Position Counters UPOS and LPOS 6 1 read-write 0 No action #0 1 INDEX pulse initializes the position counter #1 XIRQ INDEX Pulse Interrupt Request 8 1 read-write 0 No interrupt has occurred #0 1 INDEX pulse interrupt has occurred #1 XNE Use Negative Edge of INDEX Pulse 5 1 read-write 0 Use positive transition edge of INDEX pulse #0 1 Use negative transition edge of INDEX pulse #1 CTRL2 Control 2 Register 0x1E 16 read-write n 0x0 0x0 DIR Count Direction Flag 3 1 read-only 0 Last count was in the down direction #0 1 Last count was in the up direction #1 MOD Enable Modulo Counting 2 1 read-write 0 Disable modulo counting #0 1 Enable modulo counting #1 OUTCTL Output Control 9 1 read-write 0 POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). #0 1 POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read. #1 REVMOD Revolution Counter Modulus Enable 8 1 read-write 0 Use INDEX pulse to increment/decrement revolution counter (REV). #0 1 Use modulus counting roll-over/under to increment/decrement revolution counter (REV). #1 ROIE Roll-over Interrupt Enable 6 1 read-write 0 Roll-over interrupt is disabled #0 1 Roll-over interrupt is enabled #1 ROIRQ Roll-over Interrupt Request 7 1 read-write 0 No roll-over has occurred #0 1 Roll-over has occurred #1 RUIE Roll-under Interrupt Enable 4 1 read-write 0 Roll-under interrupt is disabled #0 1 Roll-under interrupt is enabled #1 RUIRQ Roll-under Interrupt Request 5 1 read-write 0 No roll-under has occurred #0 1 Roll-under has occurred #1 SABIE Simultaneous PHASEA and PHASEB Change Interrupt Enable 10 1 read-write 0 Simultaneous PHASEA and PHASEB change interrupt disabled. #0 1 Simultaneous PHASEA and PHASEB change interrupt enabled. #1 SABIRQ Simultaneous PHASEA and PHASEB Change Interrupt Request 11 1 read-write 0 No simultaneous change of PHASEA and PHASEB has occurred. #0 1 A simultaneous change of PHASEA and PHASEB has occurred. #1 UPDHLD Update Hold Registers 0 1 read-write 0 Disable updates of hold registers on rising edge of TRIGGER #0 1 Enable updates of hold registers on rising edge of TRIGGER #1 UPDPOS Update Position Registers 1 1 read-write 0 No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER #0 1 Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER #1 FILT Input Filter Register 0x2 16 read-write n 0x0 0x0 FILT_CNT Input Filter Sample Count 8 3 read-write FILT_PER Input Filter Sample Period 0 8 read-write IMR Input Monitor Register 0x1A 16 read-only n 0x0 0x0 FHOM This is the filtered version of HOME input. 4 1 read-only FIND This is the filtered version of INDEX input. 5 1 read-only FPHA This is the filtered version of PHASEA input. 7 1 read-only FPHB This is the filtered version of PHASEB input. 6 1 read-only HOME This is the raw HOME input. 0 1 read-only INDEX This is the raw INDEX input. 1 1 read-only PHA This is the raw PHASEA input. 3 1 read-only PHB This is the raw PHASEB input. 2 1 read-only LCOMP Lower Position Compare Register 0x26 16 read-write n 0x0 0x0 COMP This read/write register contains the lower (least significant) half of the position compare register 0 16 read-write LINIT Lower Initialization Register 0x18 16 read-write n 0x0 0x0 INIT This read/write register contains the value to be used to initialize the lower half of the position counter (LPOS) 0 16 read-write LMOD Lower Modulus Register 0x22 16 read-write n 0x0 0x0 MOD This read/write register contains the lower (least significant) half of the modulus register 0 16 read-write LPOS Lower Position Counter Register 0x10 16 read-write n 0x0 0x0 POS This read/write register contains the lower (least significant) half of the position counter 0 16 read-write LPOSH Lower Position Hold Register 0x14 16 read-only n 0x0 0x0 POSH This read-only register contains a snapshot of the LPOS register. 0 16 read-only POSD Position Difference Counter Register 0x6 16 read-write n 0x0 0x0 POSD This read/write register contains the position change in value occurring between each read of the position register 0 16 read-write POSDH Position Difference Hold Register 0x8 16 read-only n 0x0 0x0 POSDH This read-only register contains a snapshot of the value of the POSD register 0 16 read-only REV Revolution Counter Register 0xA 16 read-write n 0x0 0x0 REV This read/write register contains the current value of the revolution counter. 0 16 read-write REVH Revolution Hold Register 0xC 16 read-only n 0x0 0x0 REVH This read-only register contains a snapshot of the value of the REV register. 0 16 read-only TST Test Register 0x1C 16 read-write n 0x0 0x0 QDN Quadrature Decoder Negative Signal 13 1 read-write 0 Leaves quadrature decoder signal in a positive direction #0 1 Generates a negative quadrature decoder signal #1 TCE Test Counter Enable 14 1 read-write 0 Test count is not enabled #0 1 Test count is enabled #1 TEN Test Mode Enable 15 1 read-write 0 Test module is not enabled #0 1 Test module is enabled #1 TEST_COUNT These bits hold the number of quadrature advances to generate. 0 8 read-write TEST_PERIOD These bits hold the period of quadrature phase in IPBus clock cycles. 8 5 read-write UCOMP Upper Position Compare Register 0x24 16 read-write n 0x0 0x0 COMP This read/write register contains the upper (most significant) half of the position compare register 0 16 read-write UINIT Upper Initialization Register 0x16 16 read-write n 0x0 0x0 INIT This read/write register contains the value to be used to initialize the upper half of the position counter (UPOS) 0 16 read-write UMOD Upper Modulus Register 0x20 16 read-write n 0x0 0x0 MOD This read/write register contains the upper (most significant) half of the modulus register 0 16 read-write UPOS Upper Position Counter Register 0xE 16 read-write n 0x0 0x0 POS This read/write register contains the upper (most significant) half of the position counter 0 16 read-write UPOSH Upper Position Hold Register 0x12 16 read-only n 0x0 0x0 POSH This read-only register contains a snapshot of the UPOS register. 0 16 read-only WTR Watchdog Timeout Register 0x4 16 read-write n 0x0 0x0 WDOG WDOG[15:0] is a binary representation of the number of clock cycles plus one that the watchdog timer counts before timing out and optionally generating an interrupt 0 16 read-write EWM External Watchdog Monitor EWM 0x0 0x0 0x6 registers n WDOG_EWM 22 CLKCTRL Clock Control Register 0x4 8 read-write n 0x0 0x0 CLKSEL EWM has 4 possible low power clock sources for running EWM counter 0 2 read-write CLKPRESCALER Clock Prescaler Register 0x5 8 read-write n 0x0 0x0 CLK_DIV Selected low power clock source for running the EWM counter can be prescaled as below 0 8 read-write CMPH Compare High Register 0x3 8 read-write n 0x0 0x0 COMPAREH To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum service time is required 0 8 read-write CMPL Compare Low Register 0x2 8 read-write n 0x0 0x0 COMPAREL To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) minimum service time is required 0 8 read-write CTRL Control Register 0x0 8 read-write n 0x0 0x0 ASSIN EWM_in's Assertion State Select. 1 1 read-write EWMEN EWM enable. 0 1 read-write INEN Input Enable. 2 1 read-write INTEN Interrupt Enable. 3 1 read-write SERV Service Register 0x1 8 write-only n 0x0 0x0 SERVICE The EWM service mechanism requires the CPU to write two values to the SERV register: a first data byte of 0xB4, followed by a second data byte of 0x2C 0 8 write-only FB FlexBus external bus interface FB 0x0 0x0 0x64 registers n CSAR0 Chip Select Address Register 0x0 32 read-write n 0x0 0x0 BA Base Address 16 16 read-write CSAR1 Chip Select Address Register 0xC 32 read-write n 0x0 0x0 BA Base Address 16 16 read-write CSAR2 Chip Select Address Register 0x24 32 read-write n 0x0 0x0 BA Base Address 16 16 read-write CSAR3 Chip Select Address Register 0x48 32 read-write n 0x0 0x0 BA Base Address 16 16 read-write CSAR4 Chip Select Address Register 0x78 32 read-write n 0x0 0x0 BA Base Address 16 16 read-write CSAR5 Chip Select Address Register 0xB4 32 read-write n 0x0 0x0 BA Base Address 16 16 read-write CSCR0 Chip Select Control Register 0x10 32 read-write n 0x0 0x0 AA Auto-Acknowledge Enable 8 1 read-write 0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. #0 1 Enabled. Internal transfer acknowledge is asserted as specified by WS. #1 ASET Address Setup 20 2 read-write 00 Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). #00 01 Assert FB_CSn on the second rising clock edge after the address is asserted. #01 10 Assert FB_CSn on the third rising clock edge after the address is asserted. #10 11 Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ). #11 BEM Byte-Enable Mode 5 1 read-write 0 FB_BE is asserted for data write only. #0 1 FB_BE is asserted for data read and write accesses. #1 BLS Byte-Lane Shift 9 1 read-write 0 Not shifted. Data is left-aligned on FB_AD. #0 1 Shifted. Data is right-aligned on FB_AD. #1 BSTR Burst-Read Enable 4 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. #0 1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. #1 BSTW Burst-Write Enable 3 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. #0 1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS /FB_ALE is asserted. 22 1 read-write 0 Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. #0 1 Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts. #1 PS Port Size 6 2 read-write 00 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. #00 01 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. #01 1X 16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. #1x RDAH Read Address Hold or Deselect 18 2 read-write 00 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. #00 01 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. #01 10 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. #10 11 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. #11 SWS Secondary Wait States 26 6 read-write SWSEN Secondary Wait State Enable 23 1 read-write 0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. #0 1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. #1 WRAH Write Address Hold or Deselect 16 2 read-write 00 1 cycle (default for all but FB_CS0 ) #00 01 2 cycles #01 10 3 cycles #10 11 4 cycles (default for FB_CS0 ) #11 WS Wait States 10 6 read-write CSCR1 Chip Select Control Register 0x24 32 read-write n 0x0 0x0 AA Auto-Acknowledge Enable 8 1 read-write 0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. #0 1 Enabled. Internal transfer acknowledge is asserted as specified by WS. #1 ASET Address Setup 20 2 read-write 00 Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). #00 01 Assert FB_CSn on the second rising clock edge after the address is asserted. #01 10 Assert FB_CSn on the third rising clock edge after the address is asserted. #10 11 Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ). #11 BEM Byte-Enable Mode 5 1 read-write 0 FB_BE is asserted for data write only. #0 1 FB_BE is asserted for data read and write accesses. #1 BLS Byte-Lane Shift 9 1 read-write 0 Not shifted. Data is left-aligned on FB_AD. #0 1 Shifted. Data is right-aligned on FB_AD. #1 BSTR Burst-Read Enable 4 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. #0 1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. #1 BSTW Burst-Write Enable 3 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. #0 1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS /FB_ALE is asserted. 22 1 read-write 0 Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. #0 1 Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts. #1 PS Port Size 6 2 read-write 00 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. #00 01 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. #01 1X 16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. #1x RDAH Read Address Hold or Deselect 18 2 read-write 00 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. #00 01 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. #01 10 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. #10 11 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. #11 SWS Secondary Wait States 26 6 read-write SWSEN Secondary Wait State Enable 23 1 read-write 0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. #0 1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. #1 WRAH Write Address Hold or Deselect 16 2 read-write 00 1 cycle (default for all but FB_CS0 ) #00 01 2 cycles #01 10 3 cycles #10 11 4 cycles (default for FB_CS0 ) #11 WS Wait States 10 6 read-write CSCR2 Chip Select Control Register 0x44 32 read-write n 0x0 0x0 AA Auto-Acknowledge Enable 8 1 read-write 0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. #0 1 Enabled. Internal transfer acknowledge is asserted as specified by WS. #1 ASET Address Setup 20 2 read-write 00 Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). #00 01 Assert FB_CSn on the second rising clock edge after the address is asserted. #01 10 Assert FB_CSn on the third rising clock edge after the address is asserted. #10 11 Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ). #11 BEM Byte-Enable Mode 5 1 read-write 0 FB_BE is asserted for data write only. #0 1 FB_BE is asserted for data read and write accesses. #1 BLS Byte-Lane Shift 9 1 read-write 0 Not shifted. Data is left-aligned on FB_AD. #0 1 Shifted. Data is right-aligned on FB_AD. #1 BSTR Burst-Read Enable 4 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. #0 1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. #1 BSTW Burst-Write Enable 3 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. #0 1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS /FB_ALE is asserted. 22 1 read-write 0 Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. #0 1 Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts. #1 PS Port Size 6 2 read-write 00 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. #00 01 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. #01 1X 16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. #1x RDAH Read Address Hold or Deselect 18 2 read-write 00 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. #00 01 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. #01 10 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. #10 11 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. #11 SWS Secondary Wait States 26 6 read-write SWSEN Secondary Wait State Enable 23 1 read-write 0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. #0 1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. #1 WRAH Write Address Hold or Deselect 16 2 read-write 00 1 cycle (default for all but FB_CS0 ) #00 01 2 cycles #01 10 3 cycles #10 11 4 cycles (default for FB_CS0 ) #11 WS Wait States 10 6 read-write CSCR3 Chip Select Control Register 0x70 32 read-write n 0x0 0x0 AA Auto-Acknowledge Enable 8 1 read-write 0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. #0 1 Enabled. Internal transfer acknowledge is asserted as specified by WS. #1 ASET Address Setup 20 2 read-write 00 Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). #00 01 Assert FB_CSn on the second rising clock edge after the address is asserted. #01 10 Assert FB_CSn on the third rising clock edge after the address is asserted. #10 11 Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ). #11 BEM Byte-Enable Mode 5 1 read-write 0 FB_BE is asserted for data write only. #0 1 FB_BE is asserted for data read and write accesses. #1 BLS Byte-Lane Shift 9 1 read-write 0 Not shifted. Data is left-aligned on FB_AD. #0 1 Shifted. Data is right-aligned on FB_AD. #1 BSTR Burst-Read Enable 4 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. #0 1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. #1 BSTW Burst-Write Enable 3 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. #0 1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS /FB_ALE is asserted. 22 1 read-write 0 Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. #0 1 Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts. #1 PS Port Size 6 2 read-write 00 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. #00 01 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. #01 1X 16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. #1x RDAH Read Address Hold or Deselect 18 2 read-write 00 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. #00 01 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. #01 10 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. #10 11 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. #11 SWS Secondary Wait States 26 6 read-write SWSEN Secondary Wait State Enable 23 1 read-write 0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. #0 1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. #1 WRAH Write Address Hold or Deselect 16 2 read-write 00 1 cycle (default for all but FB_CS0 ) #00 01 2 cycles #01 10 3 cycles #10 11 4 cycles (default for FB_CS0 ) #11 WS Wait States 10 6 read-write CSCR4 Chip Select Control Register 0xA8 32 read-write n 0x0 0x0 AA Auto-Acknowledge Enable 8 1 read-write 0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. #0 1 Enabled. Internal transfer acknowledge is asserted as specified by WS. #1 ASET Address Setup 20 2 read-write 00 Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). #00 01 Assert FB_CSn on the second rising clock edge after the address is asserted. #01 10 Assert FB_CSn on the third rising clock edge after the address is asserted. #10 11 Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ). #11 BEM Byte-Enable Mode 5 1 read-write 0 FB_BE is asserted for data write only. #0 1 FB_BE is asserted for data read and write accesses. #1 BLS Byte-Lane Shift 9 1 read-write 0 Not shifted. Data is left-aligned on FB_AD. #0 1 Shifted. Data is right-aligned on FB_AD. #1 BSTR Burst-Read Enable 4 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. #0 1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. #1 BSTW Burst-Write Enable 3 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. #0 1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS /FB_ALE is asserted. 22 1 read-write 0 Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. #0 1 Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts. #1 PS Port Size 6 2 read-write 00 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. #00 01 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. #01 1X 16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. #1x RDAH Read Address Hold or Deselect 18 2 read-write 00 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. #00 01 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. #01 10 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. #10 11 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. #11 SWS Secondary Wait States 26 6 read-write SWSEN Secondary Wait State Enable 23 1 read-write 0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. #0 1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. #1 WRAH Write Address Hold or Deselect 16 2 read-write 00 1 cycle (default for all but FB_CS0 ) #00 01 2 cycles #01 10 3 cycles #10 11 4 cycles (default for FB_CS0 ) #11 WS Wait States 10 6 read-write CSCR5 Chip Select Control Register 0xEC 32 read-write n 0x0 0x0 AA Auto-Acknowledge Enable 8 1 read-write 0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. #0 1 Enabled. Internal transfer acknowledge is asserted as specified by WS. #1 ASET Address Setup 20 2 read-write 00 Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). #00 01 Assert FB_CSn on the second rising clock edge after the address is asserted. #01 10 Assert FB_CSn on the third rising clock edge after the address is asserted. #10 11 Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ). #11 BEM Byte-Enable Mode 5 1 read-write 0 FB_BE is asserted for data write only. #0 1 FB_BE is asserted for data read and write accesses. #1 BLS Byte-Lane Shift 9 1 read-write 0 Not shifted. Data is left-aligned on FB_AD. #0 1 Shifted. Data is right-aligned on FB_AD. #1 BSTR Burst-Read Enable 4 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. #0 1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. #1 BSTW Burst-Write Enable 3 1 read-write 0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. #0 1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS /FB_ALE is asserted. 22 1 read-write 0 Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. #0 1 Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts. #1 PS Port Size 6 2 read-write 00 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. #00 01 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. #01 1X 16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b. #1x RDAH Read Address Hold or Deselect 18 2 read-write 00 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. #00 01 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. #01 10 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. #10 11 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. #11 SWS Secondary Wait States 26 6 read-write SWSEN Secondary Wait State Enable 23 1 read-write 0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. #0 1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. #1 WRAH Write Address Hold or Deselect 16 2 read-write 00 1 cycle (default for all but FB_CS0 ) #00 01 2 cycles #01 10 3 cycles #10 11 4 cycles (default for FB_CS0 ) #11 WS Wait States 10 6 read-write CSMR0 Chip Select Mask Register 0x8 32 read-write n 0x0 0x0 BAM Base Address Mask 16 16 read-write 0 The corresponding address bit in CSAR is used in the chip-select decode. #0 1 The corresponding address bit in CSAR is a don't care in the chip-select decode. #1 V Valid 0 1 read-write 0 Chip-select is invalid. #0 1 Chip-select is valid. #1 WP Write Protect 8 1 read-write 0 Write accesses are allowed. #0 1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. #1 CSMR1 Chip Select Mask Register 0x18 32 read-write n 0x0 0x0 BAM Base Address Mask 16 16 read-write 0 The corresponding address bit in CSAR is used in the chip-select decode. #0 1 The corresponding address bit in CSAR is a don't care in the chip-select decode. #1 V Valid 0 1 read-write 0 Chip-select is invalid. #0 1 Chip-select is valid. #1 WP Write Protect 8 1 read-write 0 Write accesses are allowed. #0 1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. #1 CSMR2 Chip Select Mask Register 0x34 32 read-write n 0x0 0x0 BAM Base Address Mask 16 16 read-write 0 The corresponding address bit in CSAR is used in the chip-select decode. #0 1 The corresponding address bit in CSAR is a don't care in the chip-select decode. #1 V Valid 0 1 read-write 0 Chip-select is invalid. #0 1 Chip-select is valid. #1 WP Write Protect 8 1 read-write 0 Write accesses are allowed. #0 1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. #1 CSMR3 Chip Select Mask Register 0x5C 32 read-write n 0x0 0x0 BAM Base Address Mask 16 16 read-write 0 The corresponding address bit in CSAR is used in the chip-select decode. #0 1 The corresponding address bit in CSAR is a don't care in the chip-select decode. #1 V Valid 0 1 read-write 0 Chip-select is invalid. #0 1 Chip-select is valid. #1 WP Write Protect 8 1 read-write 0 Write accesses are allowed. #0 1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. #1 CSMR4 Chip Select Mask Register 0x90 32 read-write n 0x0 0x0 BAM Base Address Mask 16 16 read-write 0 The corresponding address bit in CSAR is used in the chip-select decode. #0 1 The corresponding address bit in CSAR is a don't care in the chip-select decode. #1 V Valid 0 1 read-write 0 Chip-select is invalid. #0 1 Chip-select is valid. #1 WP Write Protect 8 1 read-write 0 Write accesses are allowed. #0 1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. #1 CSMR5 Chip Select Mask Register 0xD0 32 read-write n 0x0 0x0 BAM Base Address Mask 16 16 read-write 0 The corresponding address bit in CSAR is used in the chip-select decode. #0 1 The corresponding address bit in CSAR is a don't care in the chip-select decode. #1 V Valid 0 1 read-write 0 Chip-select is invalid. #0 1 Chip-select is valid. #1 WP Write Protect 8 1 read-write 0 Write accesses are allowed. #0 1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. #1 CSPMCR Chip Select port Multiplexing Control Register 0x60 32 read-write n 0x0 0x0 GROUP1 FlexBus Signal Group 1 Multiplex control 28 4 read-write 0000 FB_ALE #0000 0001 FB_CS1 #0001 0010 FB_TS #0010 GROUP2 FlexBus Signal Group 2 Multiplex control 24 4 read-write 0000 FB_CS4 #0000 0001 FB_TSIZ0 #0001 0010 FB_BE_31_24 #0010 GROUP3 FlexBus Signal Group 3 Multiplex control 20 4 read-write 0000 FB_CS5 #0000 0001 FB_TSIZ1 #0001 0010 FB_BE_23_16 #0010 GROUP4 FlexBus Signal Group 4 Multiplex control 16 4 read-write 0000 FB_TBST #0000 0001 FB_CS2 #0001 0010 FB_BE_15_8 #0010 GROUP5 FlexBus Signal Group 5 Multiplex control 12 4 read-write 0000 FB_TA #0000 0001 FB_CS3 . You must also write 1b to CSCR[AA]. #0001 0010 FB_BE_7_0 . You must also write 1b to CSCR[AA]. #0010 FMC Flash Memory Controller FMC 0x0 0x0 0x8 registers n PFAPR Flash Access Protection Register 0x0 32 read-write n 0x0 0x0 M0AP Master 0 Access Protection 0 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M0PFD Master 0 Prefetch Disable 16 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M1AP Master 1 Access Protection 2 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M1PFD Master 1 Prefetch Disable 17 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M2AP Master 2 Access Protection 4 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M2PFD Master 2 Prefetch Disable 18 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M3AP Master 3 Access Protection 6 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M3PFD Master 3 Prefetch Disable 19 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 PFB0CR Flash Bank 0 Control Register 0x4 32 read-write n 0x0 0x0 B0DPE Bank 0 Data Prefetch Enable 2 1 read-write 0 Do not prefetch in response to data references. #0 1 Enable prefetches in response to data references. #1 B0IPE Bank 0 Instruction Prefetch Enable 1 1 read-write 0 Do not prefetch in response to instruction fetches. #0 1 Enable prefetches in response to instruction fetches. #1 B0MW Bank 0 Memory Width 17 2 read-only 00 32 bits #00 01 64 bits #01 10 128 bits #10 11 256 bits #11 B0RWSC Bank 0 Read Wait State Control 28 4 read-only S_INV Invalidate Prefetch Speculation Buffer 19 1 write-only 0 Speculation buffer is not affected. #0 1 Invalidate (clear) the speculation buffer. #1 FTFE Flash Memory Interface FTFE 0x0 0x0 0x14 registers n FTFE 18 Read_Collision 19 FCCOB0 Flash Common Command Object Registers 0x1A 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB1 Flash Common Command Object Registers 0x13 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB2 Flash Common Command Object Registers 0xD 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB3 Flash Common Command Object Registers 0x8 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB4 Flash Common Command Object Registers 0x40 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB5 Flash Common Command Object Registers 0x35 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB6 Flash Common Command Object Registers 0x2B 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB7 Flash Common Command Object Registers 0x22 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB8 Flash Common Command Object Registers 0x76 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB9 Flash Common Command Object Registers 0x67 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOBA Flash Common Command Object Registers 0x59 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOBB Flash Common Command Object Registers 0x4C 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCNFG Flash Configuration Register 0x1 8 read-write n 0x0 0x0 CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt disabled #0 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. #1 EEERDY This bit is reserved and always has the value 0. 0 1 read-only 0 See RAMRDY for availability of programming acceleration RAM #0 ERSAREQ Erase All Request 5 1 read-only 0 No request or request complete #0 1 Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state #1 ERSSUSP Erase Suspend 4 1 read-write 0 No suspend requested #0 1 Suspend the current Erase Flash Sector command execution #1 PFLSH FTFE configuration 2 1 read-only 1 FTFE configuration supports one program flash block #1 RAMRDY RAM Ready 1 1 read-only 0 Programming acceleration RAM is not available #0 1 Programming acceleration RAM is available #1 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write 0 Read collision error interrupt disabled #0 1 Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]). #1 FOPT Flash Option Register 0x3 8 read-only n 0x0 0x0 OPT Nonvolatile Option 0 8 read-only FPROT0 Program Flash Protection Registers 0x56 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT1 Program Flash Protection Registers 0x43 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT2 Program Flash Protection Registers 0x31 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT3 Program Flash Protection Registers 0x20 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FSEC Flash Security Register 0x2 8 read-only n 0x0 0x0 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 00 Freescale factory access granted #00 01 Freescale factory access denied #01 10 Freescale factory access denied #10 11 Freescale factory access granted #11 KEYEN Backdoor Key Security Enable 6 2 read-only 00 Backdoor key access disabled #00 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) #01 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 MEEN Mass Erase Enable Bits 4 2 read-only 00 Mass erase is enabled #00 01 Mass erase is enabled #01 10 Mass erase is disabled #10 11 Mass erase is enabled #11 SEC Flash Security 0 2 read-only 00 MCU security status is secure #00 01 MCU security status is secure #01 10 MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.) #10 11 MCU security status is secure #11 FSTAT Flash Status Register 0x0 8 read-write n 0x0 0x0 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error detected #0 1 Access error detected #1 CCIF Command Complete Interrupt Flag 7 1 read-write 0 FTFE command in progress #0 1 FTFE command has completed #1 FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation detected #0 1 Protection violation detected #1 MGSTAT0 Memory Controller Command Completion Status Flag 0 1 read-only RDCOLERR FTFE Read Collision Error Flag 6 1 read-write 0 No collision error detected #0 1 Collision error detected #1 FTFL_FlashConfig Flash configuration field FTFL_FlashConfig 0x0 0x0 0xE registers n NV_BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY3 Backdoor Comparison Key 3. 0x0 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_FOPT Non-volatile Flash Option Register 0xD 8 read-only n 0x0 0x0 FAST_INIT no description available 5 1 read-only 00 Slower initialization #0 01 Fast Initialization #1 LPBOOT no description available 0 1 read-only 00 Low-power boot #0 01 Normal boot #1 NMI_DIS no description available 2 1 read-only 00 NMI interrupts are always blocked #0 01 NMI_b pin/interrupts reset default to enabled #1 NV_FPROT0 Non-volatile P-Flash Protection 0 - High Register 0xB 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT1 Non-volatile P-Flash Protection 0 - Low Register 0xA 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT2 Non-volatile P-Flash Protection 1 - High Register 0x9 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT3 Non-volatile P-Flash Protection 1 - Low Register 0x8 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FSEC Non-volatile Flash Security Register 0xC 8 read-only n 0x0 0x0 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 10 Freescale factory access denied #10 11 Freescale factory access granted #11 KEYEN Backdoor Key Security Enable 6 2 read-only 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 MEEN no description available 4 2 read-only 10 Mass erase is disabled #10 11 Mass erase is enabled #11 SEC Flash Security 0 2 read-only 10 MCU security status is unsecure #10 11 MCU security status is secure #11 FTM0 FlexTimer Module FTM 0x0 0x0 0x9C registers n FTM0 42 C0SC Channel (n) Status And Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C1SC Channel (n) Status And Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C2SC Channel (n) Status And Control 0x48 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C2V Channel (n) Value 0x58 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C3SC Channel (n) Status And Control 0x6C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C3V Channel (n) Value 0x80 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C4SC Channel (n) Status And Control 0x98 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C4V Channel (n) Value 0xB0 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C5SC Channel (n) Status And Control 0xCC 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C5V Channel (n) Value 0xE8 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C6SC Channel (n) Status And Control 0x108 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C6V Channel (n) Value 0x128 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C7SC Channel (n) Status And Control 0x14C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C7V Channel (n) Value 0x170 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 INIT Initial Value Of The FTM Counter 0 16 read-write COMBINE Function For Linked Channels 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 NUMTOF TOF Frequency 0 5 read-write DEADTIME Deadtime Insertion Control 0x68 32 read-write n 0x0 0x0 DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write EXTTRIG FTM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write n 0x0 0x0 FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write FLTPOL FTM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FMS Fault Mode Status 0x74 32 read-write n 0x0 0x0 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 INVCTRL FTM Inverting Control 0x90 32 read-write n 0x0 0x0 INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD Modulo Value 0 16 read-write MODE Features Mode Selection 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write n 0x0 0x0 CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 POL Channels Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 PWMLOAD FTM PWM Load 0x98 32 read-write n 0x0 0x0 CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 SC Status And Control 0x0 32 read-write n 0x0 0x0 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture And Compare Status 0x50 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write n 0x0 0x0 CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 SYNC Synchronization 0x58 32 read-write n 0x0 0x0 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 FTM1 FlexTimer Module FTM 0x0 0x0 0x9C registers n FTM1 43 C0SC Channel (n) Status And Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C1SC Channel (n) Status And Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 INIT Initial Value Of The FTM Counter 0 16 read-write COMBINE Function For Linked Channels 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 NUMTOF TOF Frequency 0 5 read-write DEADTIME Deadtime Insertion Control 0x68 32 read-write n 0x0 0x0 DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write EXTTRIG FTM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write n 0x0 0x0 FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write FLTPOL FTM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FMS Fault Mode Status 0x74 32 read-write n 0x0 0x0 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 INVCTRL FTM Inverting Control 0x90 32 read-write n 0x0 0x0 INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD Modulo Value 0 16 read-write MODE Features Mode Selection 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write n 0x0 0x0 CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 POL Channels Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 PWMLOAD FTM PWM Load 0x98 32 read-write n 0x0 0x0 CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 SC Status And Control 0x0 32 read-write n 0x0 0x0 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture And Compare Status 0x50 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write n 0x0 0x0 CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 SYNC Synchronization 0x58 32 read-write n 0x0 0x0 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 FTM2 FlexTimer Module FTM 0x0 0x0 0x9C registers n FTM2 53 C0SC Channel (n) Status And Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C1SC Channel (n) Status And Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 INIT Initial Value Of The FTM Counter 0 16 read-write COMBINE Function For Linked Channels 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 NUMTOF TOF Frequency 0 5 read-write DEADTIME Deadtime Insertion Control 0x68 32 read-write n 0x0 0x0 DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write EXTTRIG FTM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write n 0x0 0x0 FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write FLTPOL FTM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FMS Fault Mode Status 0x74 32 read-write n 0x0 0x0 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 INVCTRL FTM Inverting Control 0x90 32 read-write n 0x0 0x0 INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD Modulo Value 0 16 read-write MODE Features Mode Selection 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write n 0x0 0x0 CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 POL Channels Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 PWMLOAD FTM PWM Load 0x98 32 read-write n 0x0 0x0 CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 SC Status And Control 0x0 32 read-write n 0x0 0x0 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture And Compare Status 0x50 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write n 0x0 0x0 CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 SYNC Synchronization 0x58 32 read-write n 0x0 0x0 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 FTM3 FlexTimer Module FTM 0x0 0x0 0x9C registers n FTM3 71 C0SC Channel (n) Status And Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C1SC Channel (n) Status And Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C2SC Channel (n) Status And Control 0x48 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C2V Channel (n) Value 0x58 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C3SC Channel (n) Status And Control 0x6C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C3V Channel (n) Value 0x80 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C4SC Channel (n) Status And Control 0x98 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C4V Channel (n) Value 0xB0 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C5SC Channel (n) Status And Control 0xCC 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C5V Channel (n) Value 0xE8 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C6SC Channel (n) Status And Control 0x108 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C6V Channel (n) Value 0x128 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C7SC Channel (n) Status And Control 0x14C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write ICRST FTM counter reset by the selected input capture event. 1 1 read-write 0 FTM counter is not reset when the selected channel (n) input event is detected. #0 1 FTM counter is reset when the selected channel (n) input event is detected. #1 MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C7V Channel (n) Value 0x170 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 INIT Initial Value Of The FTM Counter 0 16 read-write COMBINE Function For Linked Channels 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels For n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE1 Combine Channels For n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE2 Combine Channels For n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE3 Combine Channels For n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement Of Channel (n) For n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP1 Complement Of Channel (n) For n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP2 Complement Of Channel (n) For n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP3 Complement Of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAP0 Dual Edge Capture Mode Captures For n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP1 Dual Edge Capture Mode Captures For n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP2 Dual Edge Capture Mode Captures For n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP3 Dual Edge Capture Mode Captures For n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAPEN0 Dual Edge Capture Mode Enable For n = 0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAPEN1 Dual Edge Capture Mode Enable For n = 2 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAPEN2 Dual Edge Capture Mode Enable For n = 4 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DECAPEN3 Dual Edge Capture Mode Enable For n = 6 26 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 DTEN0 Deadtime Enable For n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN1 Deadtime Enable For n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN2 Deadtime Enable For n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN3 Deadtime Enable For n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable For n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable For n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable For n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable For n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 SYNCEN0 Synchronization Enable For n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable For n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable For n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable For n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE BDM Mode 6 2 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 NUMTOF TOF Frequency 0 5 read-write DEADTIME Deadtime Insertion Control 0x68 32 read-write n 0x0 0x0 DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write EXTTRIG FTM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write FLTCTRL Fault Control 0x7C 32 read-write n 0x0 0x0 FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write FLTPOL FTM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FMS Fault Mode Status 0x74 32 read-write n 0x0 0x0 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 INVCTRL FTM Inverting Control 0x90 32 read-write n 0x0 0x0 INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD Modulo Value 0 16 read-write MODE Features Mode Selection 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FTMEN FTM Enable 0 1 read-write 0 TPM compatibility. Free running counter and synchronization compatible with TPM. #0 1 Free running counter and synchronization are different from TPM behavior. #1 INIT Initialize The Channels Output 1 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 OUTINIT Initial State For Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 OUTMASK Output Mask 0x60 32 read-write n 0x0 0x0 CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 POL Channels Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 PWMLOAD FTM PWM Load 0x98 32 read-write n 0x0 0x0 CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 QDCTRL Quadrature Decoder Control And Status 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder mode is disabled. #0 1 Quadrature Decoder mode is enabled. #1 QUADIR FTM Counter Direction In Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 TOFDIR Timer Overflow Direction In Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 SC Status And Control 0x0 32 read-write n 0x0 0x0 CLKS Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the FTM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 FTM counter operates in Up Counting mode. #0 1 FTM counter operates in Up-Down Counting mode. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture And Compare Status 0x50 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 SWOCTRL FTM Software Output Control 0x94 32 read-write n 0x0 0x0 CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 SYNC Synchronization 0x58 32 read-write n 0x0 0x0 CNTMAX Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 CNTMIN Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 REINIT FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 HWINVC Inverting control synchronization is activated by a hardware trigger. 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWOM Output mask synchronization is activated by a hardware trigger. 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWRSTCNT FTM counter synchronization is activated by a hardware trigger. 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWSOC Software output control synchronization is activated by a hardware trigger. 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 HWWRBUF MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger. 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 SWINVC Inverting control synchronization is activated by the software trigger. 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOM Output mask synchronization is activated by the software trigger. 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWRSTCNT FTM counter synchronization is activated by the software trigger. 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWSOC Software output control synchronization is activated by the software trigger. 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SWWRBUF MOD, CNTIN, and CV registers synchronization is activated by the software trigger. 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 GPIOA General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTA 59 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 GPIOB General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTB 60 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 GPIOC General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTC 61 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 GPIOD General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTD 62 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 GPIOE General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTE 63 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 HSADC0 SAR Analog to digital converter HSADC 0x0 0x0 0xBC registers n HSADC_ERR 38 HSADC0_CCA 39 HSADC0_CCB 73 CALIB HSADCs Calibration Configuration 0xAE 16 read-write n 0x0 0x0 BYPA ADCA calibration bypass 2 1 read-write 0 ADCA block uses the calibration values to obtain the final conversion result (differential or single-ended mode) #0 1 Calibration operation is bypassed on ADCA. #1 BYPB ADCB calibration bypass 6 1 read-write 0 ADCB block uses the calibration values to obtain the final conversion result (differential or single-ended mode) #0 1 Calibration operation is bypassed on ADCB. #1 CAL_REQA Calibration Request for ADCA 3 1 write-only 0 None. #0 1 Calibration request for ADCA. #1 CAL_REQB Calibration Request for ADCB 7 1 write-only 0 Calibration is not requested. #0 1 Calibration is requested for ADCB. #1 EOCALIEA Interrupt Enable for End of Calibration on ADCA 8 1 read-write 0 Interrupt is not enabled. #0 1 Interrupt is enabled. #1 EOCALIEB Interrupt Enable for End of Calibration on ADCB 9 1 read-write 0 Interrupt is not enabled. #0 1 Interrupt is enabled. #1 REQDIFA ADCA Calibration request for differential mode 1 1 read-write 0 Calibration value calculation is not requested to ADCA. #0 1 Calibration value calculation for differential input mode is requested to be run on ADCA. #1 REQDIFB ADCB Calibration request for differential mode 5 1 read-write 0 Calibration value calculation is not requested to be run on ADCB. #0 1 Calibration value calculation for differential input mode is requested to be run onr ADCB #1 REQSINGA ADCA Calibration request for single ended mode 0 1 read-write 0 Calibration value calculation is not requested to be run on ADCA. #0 1 Calibration value calculation for single-ended input mode is requested to be run on ADCA. #1 REQSINGB ADCB Calibration request for single ended mode 4 1 read-write 0 Calibration value calculation is not requested to be run on ADCB. #0 1 Calibration value calculation for single-ended input mode is requested to be run on ADCB. #1 CALVAL_A Calibration Values for ADCA Register 0xB0 16 read-write n 0x0 0x0 CALVDIF Differential mode calibration value for ADCA 8 7 read-write CALVSING Single-ended mode calibration value for ADCA 0 7 read-write CALVAL_B Calibration Values for ADCB Register 0xB2 16 read-write n 0x0 0x0 CALVDIF Differential mode calibration value 8 7 read-write CALVSING Single-ended mode calibration value 0 7 read-write CLIST1 HSADC Channel List Register 1 0x8 16 read-write n 0x0 0x0 SAMPLE0 Sample Field 0 0 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE1 Sample Field 1 4 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE2 Sample Field 2 8 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE3 Sample Field 3 12 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 CLIST2 HSADC Channel List Register 2 0xA 16 read-write n 0x0 0x0 SAMPLE4 Sample Field 4 0 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE5 Sample Field 5 4 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE6 Sample Field 6 8 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE7 Sample Field 7 12 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 CLIST3 HSADC Channel List Register 3 0xC 16 read-write n 0x0 0x0 SAMPLE10 Sample Field 10 8 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE11 Sample Field 11 12 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE8 Sample Field 8 0 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE9 Sample Field 9 4 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 CLIST4 HSADC Channel List Register 4 0xE 16 read-write n 0x0 0x0 SAMPLE12 Sample Field 12 0 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE13 Sample Field 13 4 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE14 Sample Field 14 8 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE15 Sample Field 15 12 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7-. See Input Multiplex Function section for more details. #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 CTRL1 HSADC Control Register 1 0x0 16 read-write n 0x0 0x0 CHNCFG_L CHCNF (Channel Configure Low) bits 4 4 read-write 1xxx Inputs = ANB2-ANB3 #1xxx x0xx Inputs = ANB0-ANB1 #x0xx x1xx Inputs = ANB0-ANB1 #x1xx xx0x Inputs = ANA2-ANA3 #xx0x xx1x Inputs = ANA2-ANA3 #xx1x xxx0 Inputs = ANA0-ANA1 #xxx0 xxx1 Inputs = ANA0-ANA1 #xxx1 DMAENA DMA enable 15 1 read-write 0 DMA is not enabled. #0 1 DMA is enabled. #1 EOSIEA End Of Scan Interrupt Enable 11 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 HLMTIE High Limit Interrupt Enable 8 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 LLMTIE Low Limit Interrupt Enable 9 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 SMODE HSADC Scan Mode Control 0 3 read-write 000 Once (single) sequential #000 001 Once parallel #001 010 Loop sequential #010 011 Loop parallel #011 100 Triggered sequential #100 101 Triggered parallel (default) #101 STARTA STARTA Conversion 13 1 write-only 0 No action #0 1 Start command is issued #1 STOPA Stop 14 1 read-write 0 Normal operation #0 1 Stop mode #1 SYNCA SYNCA Enable 12 1 read-write 0 Scan is initiated by a write to CTRL1[STARTA] only #0 1 Use a SYNCA input pulse or CTRL1[STARTA] to initiate a scan #1 ZCIE Zero Crossing Interrupt Enable 10 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 CTRL2 HSADC Control Register 2 0x2 16 read-write n 0x0 0x0 CHNCFG_H CHNCFG_H (Channel Configure High) bits 7 4 read-write 1xxx Inputs = ANB6-ANB7 #1xxx x0xx Inputs = ANB4-ANB5 #x0xx x1xx Inputs = ANB4-ANB5 #x1xx xx0x Inputs = ANA6-ANA7 #xx0x xx1x Inputs = ANA6-ANA7 #xx1x xxx0 Inputs = ANA4-ANA5 #xxx0 xxx1 Inputs = ANA4-ANA5 #xxx1 DIVA Clock Divisor Select 0 6 read-write DMAENB DMA enable 15 1 read-write 0 DMA is not enabled. #0 1 DMA is enabled. #1 EOSIEB End Of Scan Interrupt Enable 11 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 SIMULT Simultaneous mode 6 1 read-write 0 Parallel scans done independently #0 1 Parallel scans done simultaneously (default) #1 STARTB STARTB Conversion 13 1 write-only 0 No action #0 1 Start command is issued #1 STOPB Stop 14 1 read-write 0 Normal operation #0 1 Stop mode #1 SYNCB SYNCB Enable 12 1 read-write 0 B converter parallel scan is initiated by a write to CTRL2[STARTB] only #0 1 Use a SYNCB input pulse or CTRL2[STARTB] to initiate a B converter parallel scan #1 CTRL3 HSADC Control Register 3 0xA8 16 read-write n 0x0 0x0 ADCRES ADCA/B Conversion Resolution 8 2 read-write 00 6-bit mode #00 01 8-bit mode #01 10 10-bit mode #10 11 12-bit mode #11 DMASRC DMA Trigger Source 6 1 read-write 0 DMA trigger source is end of scan interrupt #0 1 DMA trigger source is RDY bits #1 HILIM0 HSADC High Limit Registers 0xB8 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM1 HSADC High Limit Registers 0x116 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM10 HSADC High Limit Registers 0x4BE 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM11 HSADC High Limit Registers 0x530 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM12 HSADC High Limit Registers 0x5A4 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM13 HSADC High Limit Registers 0x61A 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM14 HSADC High Limit Registers 0x692 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM15 HSADC High Limit Registers 0x70C 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM2 HSADC High Limit Registers 0x176 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM3 HSADC High Limit Registers 0x1D8 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM4 HSADC High Limit Registers 0x23C 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM5 HSADC High Limit Registers 0x2A2 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM6 HSADC High Limit Registers 0x30A 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM7 HSADC High Limit Registers 0x374 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM8 HSADC High Limit Registers 0x3E0 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM9 HSADC High Limit Registers 0x44E 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIMSTAT HSADC High Limit Status Register 0x18 16 read-write n 0x0 0x0 HLS High Limit Status Bits 0 16 read-write LOLIM0 HSADC Low Limit Registers 0x78 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM1 HSADC Low Limit Registers 0xB6 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM10 HSADC Low Limit Registers 0x33E 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM11 HSADC Low Limit Registers 0x390 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM12 HSADC Low Limit Registers 0x3E4 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM13 HSADC Low Limit Registers 0x43A 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM14 HSADC Low Limit Registers 0x492 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM15 HSADC Low Limit Registers 0x4EC 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM2 HSADC Low Limit Registers 0xF6 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM3 HSADC Low Limit Registers 0x138 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM4 HSADC Low Limit Registers 0x17C 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM5 HSADC Low Limit Registers 0x1C2 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM6 HSADC Low Limit Registers 0x20A 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM7 HSADC Low Limit Registers 0x254 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM8 HSADC Low Limit Registers 0x2A0 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM9 HSADC Low Limit Registers 0x2EE 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIMSTAT HSADC Low Limit Status Register 0x16 16 read-write n 0x0 0x0 LLS Low Limit Status Bits 0 16 read-write MUX67_SEL MUX6_7 Selection Controls Register 0xBA 16 read-write n 0x0 0x0 CH6_SELA ADCA Channel 6 additional MUX Selector 0 3 read-write CH6_SELB ADCB Channel 6 additional MUX Selector 8 3 read-write CH7_SELA ADCA Channel 7 additional MUX Selector 4 3 read-write CH7_SELB ADCB Channel 7 additional MUX Selector 12 3 read-write OFFST0 HSADC Offset Register 0xF8 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST1 HSADC Offset Register 0x176 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST10 HSADC Offset Register 0x63E 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST11 HSADC Offset Register 0x6D0 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST12 HSADC Offset Register 0x764 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST13 HSADC Offset Register 0x7FA 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST14 HSADC Offset Register 0x892 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST15 HSADC Offset Register 0x92C 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST2 HSADC Offset Register 0x1F6 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST3 HSADC Offset Register 0x278 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST4 HSADC Offset Register 0x2FC 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST5 HSADC Offset Register 0x382 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST6 HSADC Offset Register 0x40A 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST7 HSADC Offset Register 0x494 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST8 HSADC Offset Register 0x520 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST9 HSADC Offset Register 0x5AE 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write PWR HSADC Power Control Register 0x9C 16 read-write n 0x0 0x0 APD Auto Powerdown 3 1 read-write 0 Auto Powerdown Mode is not active #0 1 Auto Powerdown Mode is active #1 ASB Auto Standby 15 1 read-write 0 Auto standby mode disabled #0 1 Auto standby mode enabled #1 PDA Manual Power Down for Converter A 0 1 read-write 0 Power Up ADC converter A #0 1 Power Down ADC converter A #1 PDB Manual Power Down for Converter B 1 1 read-write 0 Power Up ADC converter B #0 1 Power Down ADC converter B #1 PSTSA ADC Converter A Power Status 10 1 read-only 0 ADC Converter A is currently powered up #0 1 ADC Converter A is currently powered down #1 PSTSB ADC Converter B Power Status 11 1 read-only 0 ADC Converter B is currently powered up #0 1 ADC Converter B is currently powered down #1 PUDELAY Power Up Delay 4 6 read-write PWR2 HSADC Power Control Register 2 0xA6 16 read-write n 0x0 0x0 DIVB Clock Divisor Select 8 6 read-write RDY HSADC Ready Register 0x14 16 read-only n 0x0 0x0 RDY Ready Sample 0 16 read-only 0 Sample not ready or has been read #0 1 Sample ready to be read #1 RSLT0 HSADC Result Registers with sign extension 0x38 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT1 HSADC Result Registers with sign extension 0x56 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT10 HSADC Result Registers with sign extension 0x1BE 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT11 HSADC Result Registers with sign extension 0x1F0 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT12 HSADC Result Registers with sign extension 0x224 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT13 HSADC Result Registers with sign extension 0x25A 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT14 HSADC Result Registers with sign extension 0x292 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT15 HSADC Result Registers with sign extension 0x2CC 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT2 HSADC Result Registers with sign extension 0x76 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT3 HSADC Result Registers with sign extension 0x98 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT4 HSADC Result Registers with sign extension 0xBC 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT5 HSADC Result Registers with sign extension 0xE2 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT6 HSADC Result Registers with sign extension 0x10A 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT7 HSADC Result Registers with sign extension 0x134 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT8 HSADC Result Registers with sign extension 0x160 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT9 HSADC Result Registers with sign extension 0x18E 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only SAMPTIM HSADC Sampling Time Configuration Register 0xAC 16 read-write n 0x0 0x0 SAMPT_A Sampling Time for ADCA. 0 8 read-write SAMPT_B Sampling Time for ADCB. 8 8 read-write SCINTEN HSADC Scan Interrupt Enable Register 0xAA 16 read-write n 0x0 0x0 SCINTEN Scan Interrupt Enable 0 16 read-write 0 Scan interrupt is not enabled for this sample. #0 1 Scan interrupt is enabled for this sample. #1 SCTRL HSADC Scan Control Register 0xA4 16 read-write n 0x0 0x0 SC Scan Control Bits 0 16 read-write 0 Perform sample immediately after the completion of the current sample. #0 1 Delay sample until a new sync input occurs. #1 SDIS HSADC Sample Disable Register 0x10 16 read-write n 0x0 0x0 DS Disable Sample Bits 0 16 read-write 0 SAMPLEx channel is enabled for HSADC scan. #0 1 SAMPLEx channel is disabled for HSADC scan and corresponding channels after SAMPLEx will also not occur in an HSADC scan. #1 STAT HSADC Status Register 0x12 16 read-write n 0x0 0x0 CALONA HSADCA Calibration execution status 0 1 read-only 0 Calibration is not running #0 1 ADCA is running calibration conversions #1 CALONB HSADCB Calibration execution status 1 1 read-only 0 Calibration is not running #0 1 ADCB is running calibration conversions #1 CIPA Conversion in Progress 15 1 read-only 0 Idle state #0 1 A scan cycle is in progress. The HSADC will ignore all sync pulses or start commands #1 CIPB Conversion in Progress 14 1 read-only 0 Idle state #0 1 A scan cycle is in progress. The HSADC will ignore all sync pulses or start commands #1 DUMMYA Dummy conversion running on HSADCA 2 1 read-only 0 Dummy conversion is not running #0 1 Dummy conversion is running on ADCA #1 DUMMYB Dummy conversion running on HSADCB 3 1 read-only 0 Dummy conversion is not running #0 1 Dummy conversion is running on ADCB #1 EOCALIA End of Calibration on ADCA Interrupt 4 1 read-write 0 Calibration is not finished. #0 1 Calibration is finished on ADCA. The IRQ occurs if CALIB[EOCALIEA] is asserted. #1 EOCALIB End of Calibration on ADCB Interrupt 5 1 read-write 0 Calibration is not finished. #0 1 Calibration is finished on ADCB. The IRQ occurs if CALIB[EOCALIEB] is asserted. #1 EOSIA End of Scan Interrupt 11 1 read-write 0 A scan cycle has not been completed, no end of scan IRQ pending #0 1 A scan cycle has been completed, end of scan IRQ pending #1 EOSIB End of Scan Interrupt 12 1 read-write 0 A scan cycle has not been completed, no end of scan IRQ pending #0 1 A scan cycle has been completed, end of scan IRQ pending #1 HLMTI High Limit Interrupt 8 1 read-only 0 No high limit interrupt request #0 1 High limit exceeded, IRQ pending if CTRL1[HLMTIE] is set #1 LLMTI Low Limit Interrupt 9 1 read-only 0 No low limit interrupt request #0 1 Low limit exceeded, IRQ pending if CTRL1[LLMTIE] is set #1 ZCI Zero Crossing Interrupt 10 1 read-only 0 No zero crossing interrupt request #0 1 Zero crossing encountered, IRQ pending if CTRL1[ZCIE] is set #1 ZXCTRL1 HSADC Zero Crossing Control 1 Register 0x4 16 read-write n 0x0 0x0 ZCE0 Zero crossing enable 0 0 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE1 Zero crossing enable 1 2 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE2 Zero crossing enable 2 4 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE3 Zero crossing enable 3 6 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE4 Zero crossing enable 4 8 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE5 Zero crossing enable 5 10 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE6 Zero crossing enable 6 12 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE7 Zero crossing enable 7 14 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZXCTRL2 HSADC Zero Crossing Control 2 Register 0x6 16 read-write n 0x0 0x0 ZCE10 Zero crossing enable 10 4 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE11 Zero crossing enable 11 6 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE12 Zero crossing enable 12 8 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE13 Zero crossing enable 13 10 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE14 Zero crossing enable 14 12 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE15 Zero crossing enable 15 14 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE8 Zero crossing enable 8 0 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE9 Zero crossing enable 9 2 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZXSTAT HSADC Zero Crossing Status Register 0x1A 16 read-write n 0x0 0x0 ZCS Zero Crossing Status 0 16 read-write 0 Either: A sign change did not occur in a comparison between the current channelx result and the previous channelx result, or Zero crossing control is disabled for channelx in the zero crossing control register, ZXCTRL #0 1 In a comparison between the current channelx result and the previous channelx result, a sign change condition occurred as defined in the zero crossing control register (ZXCTRL) #1 HSADC1 SAR Analog to digital converter HSADC 0x0 0x0 0xBC registers n HSADC_ERR 38 HSADC1_CCA 74 HSADC1_CCB 93 CALIB HSADCs Calibration Configuration 0xAE 16 read-write n 0x0 0x0 BYPA ADCA calibration bypass 2 1 read-write 0 ADCA block uses the calibration values to obtain the final conversion result (differential or single-ended mode) #0 1 Calibration operation is bypassed on ADCA. #1 BYPB ADCB calibration bypass 6 1 read-write 0 ADCB block uses the calibration values to obtain the final conversion result (differential or single-ended mode) #0 1 Calibration operation is bypassed on ADCB. #1 CAL_REQA Calibration Request for ADCA 3 1 write-only 0 None. #0 1 Calibration request for ADCA. #1 CAL_REQB Calibration Request for ADCB 7 1 write-only 0 Calibration is not requested. #0 1 Calibration is requested for ADCB. #1 EOCALIEA Interrupt Enable for End of Calibration on ADCA 8 1 read-write 0 Interrupt is not enabled. #0 1 Interrupt is enabled. #1 EOCALIEB Interrupt Enable for End of Calibration on ADCB 9 1 read-write 0 Interrupt is not enabled. #0 1 Interrupt is enabled. #1 REQDIFA ADCA Calibration request for differential mode 1 1 read-write 0 Calibration value calculation is not requested to ADCA. #0 1 Calibration value calculation for differential input mode is requested to be run on ADCA. #1 REQDIFB ADCB Calibration request for differential mode 5 1 read-write 0 Calibration value calculation is not requested to be run on ADCB. #0 1 Calibration value calculation for differential input mode is requested to be run onr ADCB #1 REQSINGA ADCA Calibration request for single ended mode 0 1 read-write 0 Calibration value calculation is not requested to be run on ADCA. #0 1 Calibration value calculation for single-ended input mode is requested to be run on ADCA. #1 REQSINGB ADCB Calibration request for single ended mode 4 1 read-write 0 Calibration value calculation is not requested to be run on ADCB. #0 1 Calibration value calculation for single-ended input mode is requested to be run on ADCB. #1 CALVAL_A Calibration Values for ADCA Register 0xB0 16 read-write n 0x0 0x0 CALVDIF Differential mode calibration value for ADCA 8 7 read-write CALVSING Single-ended mode calibration value for ADCA 0 7 read-write CALVAL_B Calibration Values for ADCB Register 0xB2 16 read-write n 0x0 0x0 CALVDIF Differential mode calibration value 8 7 read-write CALVSING Single-ended mode calibration value 0 7 read-write CLIST1 HSADC Channel List Register 1 0x8 16 read-write n 0x0 0x0 SAMPLE0 Sample Field 0 0 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE1 Sample Field 1 4 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE2 Sample Field 2 8 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE3 Sample Field 3 12 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 CLIST2 HSADC Channel List Register 2 0xA 16 read-write n 0x0 0x0 SAMPLE4 Sample Field 4 0 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE5 Sample Field 5 4 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE6 Sample Field 6 8 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE7 Sample Field 7 12 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 CLIST3 HSADC Channel List Register 3 0xC 16 read-write n 0x0 0x0 SAMPLE10 Sample Field 10 8 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE11 Sample Field 11 12 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE8 Sample Field 8 0 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE9 Sample Field 9 4 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 CLIST4 HSADC Channel List Register 4 0xE 16 read-write n 0x0 0x0 SAMPLE12 Sample Field 12 0 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE13 Sample Field 13 4 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE14 Sample Field 14 8 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 SAMPLE15 Sample Field 15 12 4 read-write 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- #0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- #0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- #0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- #0011 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- #0100 0101 Single Ended: ANA5, Differential: ANA4+, ANA5- #0101 0110 Single Ended: ANA6, Differential: ANA6+, ANA7- #0110 0111 Single Ended: ANA7, Differential: ANA6+, ANA7- #0111 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- #1000 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- #1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- #1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- #1011 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- #1100 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- #1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7-. See Input Multiplex Function section for more details. #1110 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- #1111 CTRL1 HSADC Control Register 1 0x0 16 read-write n 0x0 0x0 CHNCFG_L CHCNF (Channel Configure Low) bits 4 4 read-write 1xxx Inputs = ANB2-ANB3 #1xxx x0xx Inputs = ANB0-ANB1 #x0xx x1xx Inputs = ANB0-ANB1 #x1xx xx0x Inputs = ANA2-ANA3 #xx0x xx1x Inputs = ANA2-ANA3 #xx1x xxx0 Inputs = ANA0-ANA1 #xxx0 xxx1 Inputs = ANA0-ANA1 #xxx1 DMAENA DMA enable 15 1 read-write 0 DMA is not enabled. #0 1 DMA is enabled. #1 EOSIEA End Of Scan Interrupt Enable 11 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 HLMTIE High Limit Interrupt Enable 8 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 LLMTIE Low Limit Interrupt Enable 9 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 SMODE HSADC Scan Mode Control 0 3 read-write 000 Once (single) sequential #000 001 Once parallel #001 010 Loop sequential #010 011 Loop parallel #011 100 Triggered sequential #100 101 Triggered parallel (default) #101 STARTA STARTA Conversion 13 1 write-only 0 No action #0 1 Start command is issued #1 STOPA Stop 14 1 read-write 0 Normal operation #0 1 Stop mode #1 SYNCA SYNCA Enable 12 1 read-write 0 Scan is initiated by a write to CTRL1[STARTA] only #0 1 Use a SYNCA input pulse or CTRL1[STARTA] to initiate a scan #1 ZCIE Zero Crossing Interrupt Enable 10 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 CTRL2 HSADC Control Register 2 0x2 16 read-write n 0x0 0x0 CHNCFG_H CHNCFG_H (Channel Configure High) bits 7 4 read-write 1xxx Inputs = ANB6-ANB7 #1xxx x0xx Inputs = ANB4-ANB5 #x0xx x1xx Inputs = ANB4-ANB5 #x1xx xx0x Inputs = ANA6-ANA7 #xx0x xx1x Inputs = ANA6-ANA7 #xx1x xxx0 Inputs = ANA4-ANA5 #xxx0 xxx1 Inputs = ANA4-ANA5 #xxx1 DIVA Clock Divisor Select 0 6 read-write DMAENB DMA enable 15 1 read-write 0 DMA is not enabled. #0 1 DMA is enabled. #1 EOSIEB End Of Scan Interrupt Enable 11 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 SIMULT Simultaneous mode 6 1 read-write 0 Parallel scans done independently #0 1 Parallel scans done simultaneously (default) #1 STARTB STARTB Conversion 13 1 write-only 0 No action #0 1 Start command is issued #1 STOPB Stop 14 1 read-write 0 Normal operation #0 1 Stop mode #1 SYNCB SYNCB Enable 12 1 read-write 0 B converter parallel scan is initiated by a write to CTRL2[STARTB] only #0 1 Use a SYNCB input pulse or CTRL2[STARTB] to initiate a B converter parallel scan #1 CTRL3 HSADC Control Register 3 0xA8 16 read-write n 0x0 0x0 ADCRES ADCA/B Conversion Resolution 8 2 read-write 00 6-bit mode #00 01 8-bit mode #01 10 10-bit mode #10 11 12-bit mode #11 DMASRC DMA Trigger Source 6 1 read-write 0 DMA trigger source is end of scan interrupt #0 1 DMA trigger source is RDY bits #1 HILIM0 HSADC High Limit Registers 0xB8 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM1 HSADC High Limit Registers 0x116 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM10 HSADC High Limit Registers 0x4BE 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM11 HSADC High Limit Registers 0x530 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM12 HSADC High Limit Registers 0x5A4 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM13 HSADC High Limit Registers 0x61A 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM14 HSADC High Limit Registers 0x692 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM15 HSADC High Limit Registers 0x70C 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM2 HSADC High Limit Registers 0x176 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM3 HSADC High Limit Registers 0x1D8 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM4 HSADC High Limit Registers 0x23C 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM5 HSADC High Limit Registers 0x2A2 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM6 HSADC High Limit Registers 0x30A 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM7 HSADC High Limit Registers 0x374 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM8 HSADC High Limit Registers 0x3E0 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIM9 HSADC High Limit Registers 0x44E 16 read-write n 0x0 0x0 HLMT High Limit Bits 3 12 read-write HILIMSTAT HSADC High Limit Status Register 0x18 16 read-write n 0x0 0x0 HLS High Limit Status Bits 0 16 read-write LOLIM0 HSADC Low Limit Registers 0x78 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM1 HSADC Low Limit Registers 0xB6 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM10 HSADC Low Limit Registers 0x33E 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM11 HSADC Low Limit Registers 0x390 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM12 HSADC Low Limit Registers 0x3E4 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM13 HSADC Low Limit Registers 0x43A 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM14 HSADC Low Limit Registers 0x492 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM15 HSADC Low Limit Registers 0x4EC 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM2 HSADC Low Limit Registers 0xF6 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM3 HSADC Low Limit Registers 0x138 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM4 HSADC Low Limit Registers 0x17C 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM5 HSADC Low Limit Registers 0x1C2 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM6 HSADC Low Limit Registers 0x20A 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM7 HSADC Low Limit Registers 0x254 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM8 HSADC Low Limit Registers 0x2A0 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIM9 HSADC Low Limit Registers 0x2EE 16 read-write n 0x0 0x0 LLMT Low Limit Bits 3 12 read-write LOLIMSTAT HSADC Low Limit Status Register 0x16 16 read-write n 0x0 0x0 LLS Low Limit Status Bits 0 16 read-write MUX67_SEL MUX6_7 Selection Controls Register 0xBA 16 read-write n 0x0 0x0 CH6_SELA ADCA Channel 6 additional MUX Selector 0 3 read-write CH6_SELB ADCB Channel 6 additional MUX Selector 8 3 read-write CH7_SELA ADCA Channel 7 additional MUX Selector 4 3 read-write CH7_SELB ADCB Channel 7 additional MUX Selector 12 3 read-write OFFST0 HSADC Offset Register 0xF8 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST1 HSADC Offset Register 0x176 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST10 HSADC Offset Register 0x63E 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST11 HSADC Offset Register 0x6D0 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST12 HSADC Offset Register 0x764 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST13 HSADC Offset Register 0x7FA 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST14 HSADC Offset Register 0x892 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST15 HSADC Offset Register 0x92C 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST2 HSADC Offset Register 0x1F6 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST3 HSADC Offset Register 0x278 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST4 HSADC Offset Register 0x2FC 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST5 HSADC Offset Register 0x382 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST6 HSADC Offset Register 0x40A 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST7 HSADC Offset Register 0x494 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST8 HSADC Offset Register 0x520 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write OFFST9 HSADC Offset Register 0x5AE 16 read-write n 0x0 0x0 OFFSET HSADC Offset Bits 3 12 read-write PWR HSADC Power Control Register 0x9C 16 read-write n 0x0 0x0 APD Auto Powerdown 3 1 read-write 0 Auto Powerdown Mode is not active #0 1 Auto Powerdown Mode is active #1 ASB Auto Standby 15 1 read-write 0 Auto standby mode disabled #0 1 Auto standby mode enabled #1 PDA Manual Power Down for Converter A 0 1 read-write 0 Power Up ADC converter A #0 1 Power Down ADC converter A #1 PDB Manual Power Down for Converter B 1 1 read-write 0 Power Up ADC converter B #0 1 Power Down ADC converter B #1 PSTSA ADC Converter A Power Status 10 1 read-only 0 ADC Converter A is currently powered up #0 1 ADC Converter A is currently powered down #1 PSTSB ADC Converter B Power Status 11 1 read-only 0 ADC Converter B is currently powered up #0 1 ADC Converter B is currently powered down #1 PUDELAY Power Up Delay 4 6 read-write PWR2 HSADC Power Control Register 2 0xA6 16 read-write n 0x0 0x0 DIVB Clock Divisor Select 8 6 read-write RDY HSADC Ready Register 0x14 16 read-only n 0x0 0x0 RDY Ready Sample 0 16 read-only 0 Sample not ready or has been read #0 1 Sample ready to be read #1 RSLT0 HSADC Result Registers with sign extension 0x38 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT1 HSADC Result Registers with sign extension 0x56 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT10 HSADC Result Registers with sign extension 0x1BE 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT11 HSADC Result Registers with sign extension 0x1F0 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT12 HSADC Result Registers with sign extension 0x224 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT13 HSADC Result Registers with sign extension 0x25A 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT14 HSADC Result Registers with sign extension 0x292 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT15 HSADC Result Registers with sign extension 0x2CC 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT2 HSADC Result Registers with sign extension 0x76 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT3 HSADC Result Registers with sign extension 0x98 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT4 HSADC Result Registers with sign extension 0xBC 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT5 HSADC Result Registers with sign extension 0xE2 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT6 HSADC Result Registers with sign extension 0x10A 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT7 HSADC Result Registers with sign extension 0x134 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT8 HSADC Result Registers with sign extension 0x160 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only RSLT9 HSADC Result Registers with sign extension 0x18E 16 read-write n 0x0 0x0 RSLT Digital Result of the Conversion 3 12 read-write SEXT Sign Extend 15 1 read-only SAMPTIM HSADC Sampling Time Configuration Register 0xAC 16 read-write n 0x0 0x0 SAMPT_A Sampling Time for ADCA. 0 8 read-write SAMPT_B Sampling Time for ADCB. 8 8 read-write SCINTEN HSADC Scan Interrupt Enable Register 0xAA 16 read-write n 0x0 0x0 SCINTEN Scan Interrupt Enable 0 16 read-write 0 Scan interrupt is not enabled for this sample. #0 1 Scan interrupt is enabled for this sample. #1 SCTRL HSADC Scan Control Register 0xA4 16 read-write n 0x0 0x0 SC Scan Control Bits 0 16 read-write 0 Perform sample immediately after the completion of the current sample. #0 1 Delay sample until a new sync input occurs. #1 SDIS HSADC Sample Disable Register 0x10 16 read-write n 0x0 0x0 DS Disable Sample Bits 0 16 read-write 0 SAMPLEx channel is enabled for HSADC scan. #0 1 SAMPLEx channel is disabled for HSADC scan and corresponding channels after SAMPLEx will also not occur in an HSADC scan. #1 STAT HSADC Status Register 0x12 16 read-write n 0x0 0x0 CALONA HSADCA Calibration execution status 0 1 read-only 0 Calibration is not running #0 1 ADCA is running calibration conversions #1 CALONB HSADCB Calibration execution status 1 1 read-only 0 Calibration is not running #0 1 ADCB is running calibration conversions #1 CIPA Conversion in Progress 15 1 read-only 0 Idle state #0 1 A scan cycle is in progress. The HSADC will ignore all sync pulses or start commands #1 CIPB Conversion in Progress 14 1 read-only 0 Idle state #0 1 A scan cycle is in progress. The HSADC will ignore all sync pulses or start commands #1 DUMMYA Dummy conversion running on HSADCA 2 1 read-only 0 Dummy conversion is not running #0 1 Dummy conversion is running on ADCA #1 DUMMYB Dummy conversion running on HSADCB 3 1 read-only 0 Dummy conversion is not running #0 1 Dummy conversion is running on ADCB #1 EOCALIA End of Calibration on ADCA Interrupt 4 1 read-write 0 Calibration is not finished. #0 1 Calibration is finished on ADCA. The IRQ occurs if CALIB[EOCALIEA] is asserted. #1 EOCALIB End of Calibration on ADCB Interrupt 5 1 read-write 0 Calibration is not finished. #0 1 Calibration is finished on ADCB. The IRQ occurs if CALIB[EOCALIEB] is asserted. #1 EOSIA End of Scan Interrupt 11 1 read-write 0 A scan cycle has not been completed, no end of scan IRQ pending #0 1 A scan cycle has been completed, end of scan IRQ pending #1 EOSIB End of Scan Interrupt 12 1 read-write 0 A scan cycle has not been completed, no end of scan IRQ pending #0 1 A scan cycle has been completed, end of scan IRQ pending #1 HLMTI High Limit Interrupt 8 1 read-only 0 No high limit interrupt request #0 1 High limit exceeded, IRQ pending if CTRL1[HLMTIE] is set #1 LLMTI Low Limit Interrupt 9 1 read-only 0 No low limit interrupt request #0 1 Low limit exceeded, IRQ pending if CTRL1[LLMTIE] is set #1 ZCI Zero Crossing Interrupt 10 1 read-only 0 No zero crossing interrupt request #0 1 Zero crossing encountered, IRQ pending if CTRL1[ZCIE] is set #1 ZXCTRL1 HSADC Zero Crossing Control 1 Register 0x4 16 read-write n 0x0 0x0 ZCE0 Zero crossing enable 0 0 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE1 Zero crossing enable 1 2 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE2 Zero crossing enable 2 4 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE3 Zero crossing enable 3 6 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE4 Zero crossing enable 4 8 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE5 Zero crossing enable 5 10 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE6 Zero crossing enable 6 12 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE7 Zero crossing enable 7 14 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZXCTRL2 HSADC Zero Crossing Control 2 Register 0x6 16 read-write n 0x0 0x0 ZCE10 Zero crossing enable 10 4 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE11 Zero crossing enable 11 6 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE12 Zero crossing enable 12 8 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE13 Zero crossing enable 13 10 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE14 Zero crossing enable 14 12 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE15 Zero crossing enable 15 14 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE8 Zero crossing enable 8 0 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZCE9 Zero crossing enable 9 2 2 read-write 00 Zero Crossing disabled #00 01 Zero Crossing enabled for positive to negative sign change #01 10 Zero Crossing enabled for negative to positive sign change #10 11 Zero Crossing enabled for any sign change #11 ZXSTAT HSADC Zero Crossing Status Register 0x1A 16 read-write n 0x0 0x0 ZCS Zero Crossing Status 0 16 read-write 0 Either: A sign change did not occur in a comparison between the current channelx result and the previous channelx result, or Zero crossing control is disabled for channelx in the zero crossing control register, ZXCTRL #0 1 In a comparison between the current channelx result and the previous channelx result, a sign change condition occurred as defined in the zero crossing control register (ZXCTRL) #1 I2C0 Inter-Integrated Circuit I2C 0x0 0x0 0xC registers n I2C0 24 A1 I2C Address Register 1 0x0 8 read-write n 0x0 0x0 AD Address 1 7 read-write A2 I2C Address Register 2 0x9 8 read-write n 0x0 0x0 SAD SMBus Address 1 7 read-write C1 I2C Control Register 1 0x2 8 read-write n 0x0 0x0 DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 RSTA Repeat START 2 1 write-only TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 C2 I2C Control Register 2 0x5 8 read-write n 0x0 0x0 AD Slave Address 0 3 read-write ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 D I2C Data I/O register 0x4 8 read-write n 0x0 0x0 DATA Data 0 8 read-write F I2C Frequency Divider register 0x1 8 read-write n 0x0 0x0 ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write n 0x0 0x0 FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 RA I2C Range Address register 0x7 8 read-write n 0x0 0x0 RAD Range Slave Address 1 7 read-write S I2C Status register 0x3 8 read-write n 0x0 0x0 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 SLTH I2C SCL Low Timeout Register High 0xA 8 read-write n 0x0 0x0 SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write n 0x0 0x0 SSLT SSLT[7:0] 0 8 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write n 0x0 0x0 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 I2C1 Inter-Integrated Circuit I2C 0x0 0x0 0xC registers n I2C1 25 A1 I2C Address Register 1 0x0 8 read-write n 0x0 0x0 AD Address 1 7 read-write A2 I2C Address Register 2 0x9 8 read-write n 0x0 0x0 SAD SMBus Address 1 7 read-write C1 I2C Control Register 1 0x2 8 read-write n 0x0 0x0 DMAEN DMA Enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 IICEN I2C Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 IICIE I2C Interrupt Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 MST Master Mode Select 5 1 read-write 0 Slave mode #0 1 Master mode #1 RSTA Repeat START 2 1 write-only TX Transmit Mode Select 4 1 read-write 0 Receive #0 1 Transmit #1 TXAK Transmit Acknowledge Enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). #0 1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). #1 WUEN Wakeup Enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 C2 I2C Control Register 2 0x5 8 read-write n 0x0 0x0 AD Slave Address 0 3 read-write ADEXT Address Extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General Call Address Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 HDRS High Drive Select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 RMEN Range Address Matching Enable 3 1 read-write 0 Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave Baud Rate Control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 D I2C Data I/O register 0x4 8 read-write n 0x0 0x0 DATA Data 0 8 read-write F I2C Frequency Divider register 0x1 8 read-write n 0x0 0x0 ICR ClockRate 0 6 read-write MULT Multiplier Factor 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 FLT I2C Programmable Input Glitch Filter Register 0x6 8 read-write n 0x0 0x0 FLT I2C Programmable Filter Factor 0 4 read-write 0 No filter/bypass #0000 SHEN Stop Hold Enable 7 1 read-write 0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated. #0 1 Stop holdoff is enabled. #1 SSIE I2C Bus Stop or Start Interrupt Enable 5 1 read-write 0 Stop or start detection interrupt is disabled #0 1 Stop or start detection interrupt is enabled #1 STARTF I2C Bus Start Detect Flag 4 1 read-write 0 No start happens on I2C bus #0 1 Start detected on I2C bus #1 STOPF I2C Bus Stop Detect Flag 6 1 read-write 0 No stop happens on I2C bus #0 1 Stop detected on I2C bus #1 RA I2C Range Address register 0x7 8 read-write n 0x0 0x0 RAD Range Slave Address 1 7 read-write S I2C Status register 0x3 8 read-write n 0x0 0x0 ARBL Arbitration Lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus Busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed As A Slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 IICIF Interrupt Flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 RAM Range Address Match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 RXAK Receive Acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 SRW Slave Read/Write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 TCF Transfer Complete Flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 SLTH I2C SCL Low Timeout Register High 0xA 8 read-write n 0x0 0x0 SSLT SSLT[15:8] 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write n 0x0 0x0 SSLT SSLT[7:0] 0 8 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write n 0x0 0x0 ALERTEN SMBus Alert Response Address Enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK Enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 SHTF1 SCL High Timeout Flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SHTF2 SCL High Timeout Flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF2IE SHTF2 Interrupt Enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SIICAEN Second I2C Address Enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 SLTF SCL Low Timeout Flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout Counter Clock Select 4 1 read-write 0 Timeout counter counts at the frequency of the I2C module clock / 64 #0 1 Timeout counter counts at the frequency of the I2C module clock #1 LLWU Low leakage wakeup unit LLWU 0x0 0x0 0x10 registers n LLWU 21 FILT1 LLWU Pin Filter 1 register 0xE 8 read-write n 0x0 0x0 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILTSEL Filter Pin Select 0 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILT2 LLWU Pin Filter 2 register 0xF 8 read-write n 0x0 0x0 FILTE Digital Filter On External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 2 was not a wakeup source #0 1 Pin Filter 2 was a wakeup source #1 FILTSEL Filter Pin Select 0 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 ME LLWU Module Enable register 0x8 8 read-write n 0x0 0x0 WUME0 Wakeup Module Enable For Module 0 0 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME1 Wakeup Module Enable for Module 1 1 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME2 Wakeup Module Enable For Module 2 2 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME3 Wakeup Module Enable For Module 3 3 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME4 Wakeup Module Enable For Module 4 4 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME5 Wakeup Module Enable For Module 5 5 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME6 Wakeup Module Enable For Module 6 6 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME7 Wakeup Module Enable For Module 7 7 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 MF5 LLWU Module Flag 5 register 0xD 8 read-only n 0x0 0x0 MWUF0 Wakeup flag For module 0 0 1 read-only 0 Module 0 input was not a wakeup source #0 1 Module 0 input was a wakeup source #1 MWUF1 Wakeup flag For module 1 1 1 read-only 0 Module 1 input was not a wakeup source #0 1 Module 1 input was a wakeup source #1 MWUF2 Wakeup flag For module 2 2 1 read-only 0 Module 2 input was not a wakeup source #0 1 Module 2 input was a wakeup source #1 MWUF3 Wakeup flag For module 3 3 1 read-only 0 Module 3 input was not a wakeup source #0 1 Module 3 input was a wakeup source #1 MWUF4 Wakeup flag For module 4 4 1 read-only 0 Module 4 input was not a wakeup source #0 1 Module 4 input was a wakeup source #1 MWUF5 Wakeup flag For module 5 5 1 read-only 0 Module 5 input was not a wakeup source #0 1 Module 5 input was a wakeup source #1 MWUF6 Wakeup flag For module 6 6 1 read-only 0 Module 6 input was not a wakeup source #0 1 Module 6 input was a wakeup source #1 MWUF7 Wakeup flag For module 7 7 1 read-only 0 Module 7 input was not a wakeup source #0 1 Module 7 input was a wakeup source #1 PE1 LLWU Pin Enable 1 register 0x0 8 read-write n 0x0 0x0 WUPE0 Wakeup Pin Enable For LLWU_P0 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE1 Wakeup Pin Enable For LLWU_P1 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE2 Wakeup Pin Enable For LLWU_P2 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE3 Wakeup Pin Enable For LLWU_P3 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE2 LLWU Pin Enable 2 register 0x1 8 read-write n 0x0 0x0 WUPE4 Wakeup Pin Enable For LLWU_P4 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE5 Wakeup Pin Enable For LLWU_P5 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE6 Wakeup Pin Enable For LLWU_P6 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE7 Wakeup Pin Enable For LLWU_P7 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE3 LLWU Pin Enable 3 register 0x2 8 read-write n 0x0 0x0 WUPE10 Wakeup Pin Enable For LLWU_P10 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE11 Wakeup Pin Enable For LLWU_P11 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE8 Wakeup Pin Enable For LLWU_P8 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE9 Wakeup Pin Enable For LLWU_P9 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE4 LLWU Pin Enable 4 register 0x3 8 read-write n 0x0 0x0 WUPE12 Wakeup Pin Enable For LLWU_P12 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE13 Wakeup Pin Enable For LLWU_P13 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE14 Wakeup Pin Enable For LLWU_P14 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE15 Wakeup Pin Enable For LLWU_P15 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE5 LLWU Pin Enable 5 register 0x4 8 read-write n 0x0 0x0 WUPE16 Wakeup Pin Enable For LLWU_P16 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE17 Wakeup Pin Enable For LLWU_P17 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE18 Wakeup Pin Enable For LLWU_P18 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE19 Wakeup Pin Enable For LLWU_P19 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE6 LLWU Pin Enable 6 register 0x5 8 read-write n 0x0 0x0 WUPE20 Wakeup Pin Enable For LLWU_P20 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE21 Wakeup Pin Enable For LLWU_P21 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE22 Wakeup Pin Enable For LLWU_P22 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE23 Wakeup Pin Enable For LLWU_P23 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE7 LLWU Pin Enable 7 register 0x6 8 read-write n 0x0 0x0 WUPE24 Wakeup Pin Enable For LLWU_P24 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE25 Wakeup Pin Enable For LLWU_P25 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE26 Wakeup Pin Enable For LLWU_P26 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE27 Wakeup Pin Enable For LLWU_P27 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE8 LLWU Pin Enable 8 register 0x7 8 read-write n 0x0 0x0 WUPE28 Wakeup Pin Enable For LLWU_P28 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE29 Wakeup Pin Enable For LLWU_P29 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE30 Wakeup Pin Enable For LLWU_P30 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE31 Wakeup Pin Enable For LLWU_P31 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PF1 LLWU Pin Flag 1 register 0x9 8 read-write n 0x0 0x0 WUF0 Wakeup Flag For LLWU_P0 0 1 read-write 0 LLWU_P0 input was not a wakeup source #0 1 LLWU_P0 input was a wakeup source #1 WUF1 Wakeup Flag For LLWU_P1 1 1 read-write 0 LLWU_P1 input was not a wakeup source #0 1 LLWU_P1 input was a wakeup source #1 WUF2 Wakeup Flag For LLWU_P2 2 1 read-write 0 LLWU_P2 input was not a wakeup source #0 1 LLWU_P2 input was a wakeup source #1 WUF3 Wakeup Flag For LLWU_P3 3 1 read-write 0 LLWU_P3 input was not a wakeup source #0 1 LLWU_P3 input was a wakeup source #1 WUF4 Wakeup Flag For LLWU_P4 4 1 read-write 0 LLWU_P4 input was not a wakeup source #0 1 LLWU_P4 input was a wakeup source #1 WUF5 Wakeup Flag For LLWU_P5 5 1 read-write 0 LLWU_P5 input was not a wakeup source #0 1 LLWU_P5 input was a wakeup source #1 WUF6 Wakeup Flag For LLWU_P6 6 1 read-write 0 LLWU_P6 input was not a wakeup source #0 1 LLWU_P6 input was a wakeup source #1 WUF7 Wakeup Flag For LLWU_P7 7 1 read-write 0 LLWU_P7 input was not a wakeup source #0 1 LLWU_P7 input was a wakeup source #1 PF2 LLWU Pin Flag 2 register 0xA 8 read-write n 0x0 0x0 WUF10 Wakeup Flag For LLWU_P10 2 1 read-write 0 LLWU_P10 input was not a wakeup source #0 1 LLWU_P10 input was a wakeup source #1 WUF11 Wakeup Flag For LLWU_P11 3 1 read-write 0 LLWU_P11 input was not a wakeup source #0 1 LLWU_P11 input was a wakeup source #1 WUF12 Wakeup Flag For LLWU_P12 4 1 read-write 0 LLWU_P12 input was not a wakeup source #0 1 LLWU_P12 input was a wakeup source #1 WUF13 Wakeup Flag For LLWU_P13 5 1 read-write 0 LLWU_P13 input was not a wakeup source #0 1 LLWU_P13 input was a wakeup source #1 WUF14 Wakeup Flag For LLWU_P14 6 1 read-write 0 LLWU_P14 input was not a wakeup source #0 1 LLWU_P14 input was a wakeup source #1 WUF15 Wakeup Flag For LLWU_P15 7 1 read-write 0 LLWU_P15 input was not a wakeup source #0 1 LLWU_P15 input was a wakeup source #1 WUF8 Wakeup Flag For LLWU_P8 0 1 read-write 0 LLWU_P8 input was not a wakeup source #0 1 LLWU_P8 input was a wakeup source #1 WUF9 Wakeup Flag For LLWU_P9 1 1 read-write 0 LLWU_P9 input was not a wakeup source #0 1 LLWU_P9 input was a wakeup source #1 PF3 LLWU Pin Flag 3 register 0xB 8 read-write n 0x0 0x0 WUF16 Wakeup Flag For LLWU_P16 0 1 read-write 0 LLWU_P16 input was not a wakeup source #0 1 LLWU_P16 input was a wakeup source #1 WUF17 Wakeup Flag For LLWU_P17 1 1 read-write 0 LLWU_P17 input was not a wakeup source #0 1 LLWU_P17 input was a wakeup source #1 WUF18 Wakeup Flag For LLWU_P18 2 1 read-write 0 LLWU_P18 input was not a wakeup source #0 1 LLWU_P18 input was a wakeup source #1 WUF19 Wakeup Flag For LLWU_P19 3 1 read-write 0 LLWU_P19 input was not a wakeup source #0 1 LLWU_P19 input was a wakeup source #1 WUF20 Wakeup Flag For LLWU_P20 4 1 read-write 0 LLWU_P20 input was not a wakeup source #0 1 LLWU_P20 input was a wakeup source #1 WUF21 Wakeup Flag For LLWU_P21 5 1 read-write 0 LLWU_P21 input was not a wakeup source #0 1 LLWU_P21 input was a wakeup source #1 WUF22 Wakeup Flag For LLWU_P22 6 1 read-write 0 LLWU_P22 input was not a wakeup source #0 1 LLWU_P22 input was a wakeup source #1 WUF23 Wakeup Flag For LLWU_P23 7 1 read-write 0 LLWU_P23 input was not a wakeup source #0 1 LLWU_P23 input was a wakeup source #1 PF4 LLWU Pin Flag 4 register 0xC 8 read-write n 0x0 0x0 WUF24 Wakeup Flag For LLWU_P24 0 1 read-write 0 LLWU_P24 input was not a wakeup source #0 1 LLWU_P24 input was a wakeup source #1 WUF25 Wakeup Flag For LLWU_P25 1 1 read-write 0 LLWU_P25 input was not a wakeup source #0 1 LLWU_P25 input was a wakeup source #1 WUF26 Wakeup Flag For LLWU_P26 2 1 read-write 0 LLWU_P26 input was not a wakeup source #0 1 LLWU_P26 input was a wakeup source #1 WUF27 Wakeup Flag For LLWU_P27 3 1 read-write 0 LLWU_P27 input was not a wakeup source #0 1 LLWU_P27 input was a wakeup source #1 WUF28 Wakeup Flag For LLWU_P28 4 1 read-write 0 LLWU_P28 input was not a wakeup source #0 1 LLWU_P28 input was a wakeup source #1 WUF29 Wakeup Flag For LLWU_P29 5 1 read-write 0 LLWU_P29 input was not a wakeup source #0 1 LLWU_P29 input was a wakeup source #1 WUF30 Wakeup Flag For LLWU_P30 6 1 read-write 0 LLWU_P30 input was not a wakeup source #0 1 LLWU_P30 input was a wakeup source #1 WUF31 Wakeup Flag For LLWU_P31 7 1 read-write 0 LLWU_P31 input was not a wakeup source #0 1 LLWU_P31 input was a wakeup source #1 LPTMR0 Low Power Timer LPTMR0 0x0 0x0 0x10 registers n LPTMR0 58 CMR Low Power Timer Compare Register 0x8 32 read-write n 0x0 0x0 COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write n 0x0 0x0 COUNTER Counter Value 0 16 read-write CSR Low Power Timer Control Status Register 0x0 32 read-write n 0x0 0x0 TCF Timer Compare Flag 7 1 read-write 0 The value of CNR is not equal to CMR and increments. #0 1 The value of CNR is equal to CMR and increments. #1 TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TFC Timer Free-Running Counter 2 1 read-write 0 CNR is reset whenever TCF is set. #0 1 CNR is reset on overflow. #1 TIE Timer Interrupt Enable 6 1 read-write 0 Timer interrupt disabled. #0 1 Timer interrupt enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. #0 1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 PSR Low Power Timer Prescale Register 0x4 32 read-write n 0x0 0x0 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/glitch filter is enabled. #0 1 Prescaler/glitch filter is bypassed. #1 PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected. #00 01 Prescaler/glitch filter clock 1 selected. #01 10 Prescaler/glitch filter clock 2 selected. #10 11 Prescaler/glitch filter clock 3 selected. #11 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. #1111 MCG Multipurpose Clock Generator module MCG 0x0 0x0 0xE registers n MCG 57 ATCVH MCG Auto Trim Compare Value High Register 0xA 8 read-write n 0x0 0x0 ATCVH ATM Compare Value High 0 8 read-write ATCVL MCG Auto Trim Compare Value Low Register 0xB 8 read-write n 0x0 0x0 ATCVL ATM Compare Value Low 0 8 read-write C1 MCG Control 1 Register 0x0 8 read-write n 0x0 0x0 CLKS Clock Source Select 6 2 read-write 00 Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Reserved. #11 FRDIV FLL External Reference Divider 3 3 read-write 000 If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. #000 001 If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. #001 010 If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. #010 011 If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. #011 100 If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. #100 101 If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. #101 110 If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . #110 111 If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . #111 IRCLKEN Internal Reference Clock Enable 1 1 read-write 0 MCGIRCLK inactive. #0 1 MCGIRCLK active. #1 IREFS Internal Reference Select 2 1 read-write 0 External reference clock is selected. #0 1 The slow internal reference clock is selected. #1 IREFSTEN Internal Reference Stop Enable 0 1 read-write 0 Internal reference clock is disabled in Stop mode. #0 1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. #1 C2 MCG Control 2 Register 0x1 8 read-write n 0x0 0x0 EREFS External Reference Select 2 1 read-write 0 External reference clock requested. #0 1 Oscillator requested. #1 FCFTRIM Fast Internal Reference Clock Fine Trim 6 1 read-write HGO High Gain Oscillator Select 3 1 read-write 0 Configure crystal oscillator for low-power operation. #0 1 Configure crystal oscillator for high-gain operation. #1 IRCS Internal Reference Clock Select 0 1 read-write 0 Slow internal reference clock selected. #0 1 Fast internal reference clock selected. #1 LOCRE0 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of OSC0 external reference clock. #0 1 Generate a reset request on a loss of OSC0 external reference clock. #1 LP Low Power Select 1 1 read-write 0 FLL or PLL is not disabled in bypass modes. #0 1 FLL or PLL is disabled in bypass modes (lower power) #1 RANGE Frequency Range Select 4 2 read-write 00 Encoding 0 - Low frequency range selected for the crystal oscillator . #00 01 Encoding 1 - High frequency range selected for the crystal oscillator . #01 1X Encoding 2 - Very high frequency range selected for the crystal oscillator . #1x C3 MCG Control 3 Register 0x2 8 read-write n 0x0 0x0 SCTRIM Slow Internal Reference Clock Trim Setting 0 8 read-write C4 MCG Control 4 Register 0x3 8 read-write n 0x0 0x0 DMX32 DCO Maximum Frequency with 32.768 kHz Reference 7 1 read-write 0 DCO has a default range of 25%. #0 1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference. #1 DRST_DRS DCO Range Select 5 2 read-write 00 Encoding 0 - Low range (reset default). #00 01 Encoding 1 - Mid range. #01 10 Encoding 2 - Mid-high range. #10 11 Encoding 3 - High range. #11 FCTRIM Fast Internal Reference Clock Trim Setting 1 4 read-write SCFTRIM Slow Internal Reference Clock Fine Trim 0 1 read-write C5 MCG Control 5 Register 0x4 8 read-write n 0x0 0x0 PLLCLKEN PLL Clock Enable 6 1 read-write 0 MCGPLLCLK is inactive. #0 1 MCGPLLCLK is active. #1 PLLSTEN PLL Stop Enable 5 1 read-write 0 MCGPLLCLK and MCGPLLCLK2X are disabled in any of the Stop modes. #0 1 MCGPLLCLK and MCGPLLCLK2X are enabled if system is in Normal Stop mode. #1 PRDIV PLL External Reference Divider 0 3 read-write 0 Divide Factor is 1 #000 1 Divide Factor is 2 #001 2 Divide Factor is 3 #010 3 Divide Factor is 4 #011 4 Divide Factor is 5 #100 5 Divide Factor is 6 #101 6 Divide Factor is 7 #110 7 Divide Factor is 8 #111 C6 MCG Control 6 Register 0x5 8 read-write n 0x0 0x0 CME0 Clock Monitor Enable 5 1 read-write 0 External clock monitor is disabled for OSC0. #0 1 External clock monitor is enabled for OSC0. #1 LOLIE0 Loss of Lock Interrrupt Enable 7 1 read-write 0 No interrupt request is generated on loss of lock. #0 1 Generate an interrupt request on loss of lock. #1 PLLS PLL Select 6 1 read-write 0 FLL is selected. #0 1 PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 8-16 MHz prior to setting the PLLS bit). #1 VDIV VCO Divider 0 5 read-write 0 Multiply Factor is 16 #00000 1 Multiply Factor is 17 #00001 2 Multiply Factor is 18 #00010 3 Multiply Factor is 19 #00011 4 Multiply Factor is 20 #00100 5 Multiply Factor is 21 #00101 6 Multiply Factor is 22 #00110 7 Multiply Factor is 23 #00111 8 Multiply Factor is 24 #01000 9 Multiply Factor is 25 #01001 10 Multiply Factor is 26 #01010 11 Multiply Factor is 27 #01011 12 Multiply Factor is 28 #01100 13 Multiply Factor is 29 #01101 14 Multiply Factor is 30 #01110 15 Multiply Factor is 31 #01111 16 Multiply Factor is 32 #10000 17 Multiply Factor is 33 #10001 18 Multiply Factor is 34 #10010 19 Multiply Factor is 35 #10011 20 Multiply Factor is 36 #10100 21 Multiply Factor is 37 #10101 22 Multiply Factor is 38 #10110 23 Multiply Factor is 39 #10111 24 Multiply Factor is 40 #11000 25 Multiply Factor is 41 #11001 26 Multiply Factor is 42 #11010 27 Multiply Factor is 43 #11011 28 Multiply Factor is 44 #11100 29 Multiply Factor is 45 #11101 30 Multiply Factor is 46 #11110 31 Multiply Factor is 47 #11111 C8 MCG Control 8 Register 0xD 8 read-write n 0x0 0x0 LOLRE PLL Loss of Lock Reset Enable 6 1 read-write 0 Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request. #0 1 Generate a reset request on a PLL loss of lock indication. #1 S MCG Status Register 0x6 8 read-write n 0x0 0x0 CLKST Clock Mode Status 2 2 read-only 00 Encoding 0 - Output of the FLL is selected (reset default). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Output of the PLL is selected. #11 IRCST Internal Reference Clock Status 0 1 read-only 0 Source of internal reference clock is the slow clock (32 kHz IRC). #0 1 Source of internal reference clock is the fast clock (4 MHz IRC). #1 IREFST Internal Reference Status 4 1 read-only 0 Source of FLL reference clock is the external reference clock. #0 1 Source of FLL reference clock is the internal reference clock. #1 LOCK0 Lock Status 6 1 read-only 0 PLL is currently unlocked. #0 1 PLL is currently locked. #1 LOLS0 Loss of Lock Status 7 1 read-write 0 PLL has not lost lock since LOLS 0 was last cleared. #0 1 PLL has lost lock since LOLS 0 was last cleared. #1 OSCINIT0 OSC Initialization 1 1 read-only PLLST PLL Select Status 5 1 read-only 0 Source of PLLS clock is FLL clock. #0 1 Source of PLLS clock is PLL output clock. #1 SC MCG Status and Control Register 0x8 8 read-write n 0x0 0x0 ATME Automatic Trim Machine Enable 7 1 read-write 0 Auto Trim Machine disabled. #0 1 Auto Trim Machine enabled. #1 ATMF Automatic Trim Machine Fail Flag 5 1 read-write 0 Automatic Trim Machine completed normally. #0 1 Automatic Trim Machine failed. #1 ATMS Automatic Trim Machine Select 6 1 read-write 0 32 kHz Internal Reference Clock selected. #0 1 4 MHz Internal Reference Clock selected. #1 FCRDIV Fast Clock Internal Reference Divider 1 3 read-write 000 Divide Factor is 1 #000 001 Divide Factor is 2. #001 010 Divide Factor is 4. #010 011 Divide Factor is 8. #011 100 Divide Factor is 16 #100 101 Divide Factor is 32 #101 110 Divide Factor is 64 #110 111 Divide Factor is 128. #111 FLTPRSRV FLL Filter Preserve Enable 4 1 read-write 0 FLL filter and FLL frequency will reset on changes to currect clock mode. #0 1 Fll filter and FLL frequency retain their previous values during new clock mode change. #1 LOCS0 OSC0 Loss of Clock Status 0 1 read-write 0 Loss of OSC0 has not occurred. #0 1 Loss of OSC0 has occurred. #1 MCM Core Platform Miscellaneous Control Module MCM 0x0 0x0 0x414 registers n MCM 17 CPO Compute Only Operation Control Register 0x34 32 read-write n 0x0 0x0 CPOACK Compute Only Operation acknowledge 1 1 read-only 0 Compute only operation entry has not completed or compute only operation exit has completed. #0 1 Compute only operation entry has completed or compute only operation exit has not completed. #1 CPOREQ Compute Only Operation request 0 1 read-write 0 Request is cleared. #0 1 Request Compute Only Operation. #1 CR Control Register 0xC 32 read-write n 0x0 0x0 AHBSPRI AHB Slave Interface Priority 27 1 read-write 0 SW accesses take priority over AHBS accesses #0 1 AHBS accesses take priority over SW accesses #1 ISCR Interrupt Status and Control Register 0x10 32 read-write n 0x0 0x0 FDZC FPU divide-by-zero interrupt status 9 1 read-only 0 No interrupt #0 1 Interrupt has occurred #1 FDZCE FPU divide-by-zero interrupt enable 25 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FIDC FPU input denormal interrupt status 15 1 read-only 0 No interrupt #0 1 Interrupt has occured #1 FIDCE FPU input denormal interrupt enable 31 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FIOC FPU invalid operation interrupt status 8 1 read-only 0 No interrupt #0 1 Interrupt has occurred #1 FIOCE FPU invalid operation interrupt enable 24 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FIXC FPU inexact interrupt status 12 1 read-only 0 No interrupt #0 1 Interrupt has occured #1 FIXCE FPU inexact interrupt enable 28 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FOFC FPU overflow interrupt status 10 1 read-only 0 No interrupt #0 1 Interrupt has occurred #1 FOFCE FPU overflow interrupt enable 26 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FUFC FPU underflow interrupt status 11 1 read-only 0 No interrupt #0 1 Interrupt has occurred #1 FUFCE FPU underflow interrupt enable 27 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 LMEM0 Local Memory General Descriptor Register 0x800 32 read-only n 0x0 0x0 LMEM_Size Defines the local memory size 24 4 read-only 0100 8KB #0100 0101 16KB #0101 0111 64KB #0111 LMEM_Type Defines the type of local memory 13 3 read-only 000 ITCM (Instruction Tightly Coupled Memory) #000 001 DTCM (Data Tightly Coupled Memory) #001 010 Instruction Cache #010 011 Data Cache #011 LMEM_Valid Defines whether the local memory is present 31 1 read-only 0 Local memory not present #0 1 Local memory present #1 LMEM_Ways Defines the ways of set associative 20 4 read-only 0000 Reserved (not applicable) #0000 0010 2-way set associative #0010 0100 4-way set associative #0100 LMEM_Width Defines the local memory bit width 17 3 read-only 010 32-bits #010 011 64-bits #011 LMEM1 Local Memory General Descriptor Register 0xC04 32 read-only n 0x0 0x0 LMEM_Size Defines the local memory size 24 4 read-only 0100 8KB #0100 0101 16KB #0101 0111 64KB #0111 LMEM_Type Defines the type of local memory 13 3 read-only 000 ITCM (Instruction Tightly Coupled Memory) #000 001 DTCM (Data Tightly Coupled Memory) #001 010 Instruction Cache #010 011 Data Cache #011 LMEM_Valid Defines whether the local memory is present 31 1 read-only 0 Local memory not present #0 1 Local memory present #1 LMEM_Ways Defines the ways of set associative 20 4 read-only 0000 Reserved (not applicable) #0000 0010 2-way set associative #0010 0100 4-way set associative #0100 LMEM_Width Defines the local memory bit width 17 3 read-only 010 32-bits #010 011 64-bits #011 LMEM2 Local Memory General Descriptor Register 0x100C 32 read-only n 0x0 0x0 LMEM_Size Defines the local memory size 24 4 read-only 0100 8KB #0100 0101 16KB #0101 0111 64KB #0111 LMEM_Type Defines the type of local memory 13 3 read-only 000 ITCM (Instruction Tightly Coupled Memory) #000 001 DTCM (Data Tightly Coupled Memory) #001 010 Instruction Cache #010 011 Data Cache #011 LMEM_Valid Defines whether the local memory is present 31 1 read-only 0 Local memory not present #0 1 Local memory present #1 LMEM_Ways Defines the ways of set associative 20 4 read-only 0000 Reserved (not applicable) #0000 0010 2-way set associative #0010 0100 4-way set associative #0100 LMEM_Width Defines the local memory bit width 17 3 read-only 010 32-bits #010 011 64-bits #011 LMEM3 Local Memory General Descriptor Register 0x1418 32 read-only n 0x0 0x0 LMEM_Size Defines the local memory size 24 4 read-only 0100 8KB #0100 0101 16KB #0101 0111 64KB #0111 LMEM_Type Defines the type of local memory 13 3 read-only 000 ITCM (Instruction Tightly Coupled Memory) #000 001 DTCM (Data Tightly Coupled Memory) #001 010 Instruction Cache #010 011 Data Cache #011 LMEM_Valid Defines whether the local memory is present 31 1 read-only 0 Local memory not present #0 1 Local memory present #1 LMEM_Ways Defines the ways of set associative 20 4 read-only 0000 Reserved (not applicable) #0000 0010 2-way set associative #0010 0100 4-way set associative #0100 LMEM_Width Defines the local memory bit width 17 3 read-only 010 32-bits #010 011 64-bits #011 LMEM4 Local Memory General Descriptor Register 0x1828 32 read-only n 0x0 0x0 LMEM_Size Defines the local memory size 24 4 read-only 0100 8KB #0100 0101 16KB #0101 0111 64KB #0111 LMEM_Type Defines the type of local memory 13 3 read-only 000 ITCM (Instruction Tightly Coupled Memory) #000 001 DTCM (Data Tightly Coupled Memory) #001 010 Instruction Cache #010 011 Data Cache #011 LMEM_Valid Defines whether the local memory is present 31 1 read-only 0 Local memory not present #0 1 Local memory present #1 LMEM_Ways Defines the ways of set associative 20 4 read-only 0000 Reserved (not applicable) #0000 0010 2-way set associative #0010 0100 4-way set associative #0100 LMEM_Width Defines the local memory bit width 17 3 read-only 010 32-bits #010 011 64-bits #011 PCT Processor core type 0x0 32 read-only n 0x0 0x0 PCT This MCM design supports the ARM Cortex M7 core. 16 16 read-only PLREV Platform revision 0 16 read-only MPU Memory protection unit MPU 0x0 0x0 0x830 registers n CESR Control/Error Status Register 0x0 32 read-write n 0x0 0x0 HRL Hardware Revision Level 16 4 read-only NRGD Number Of Region Descriptors 8 4 read-only 0000 8 region descriptors #0000 0001 12 region descriptors #0001 0010 16 region descriptors #0010 NSP Number Of Slave Ports 12 4 read-only SPERR Slave Port n Error 27 5 read-write 0 No error has occurred for slave port n. #00000 1 An error has occurred for slave port n. #00001 VLD Valid 0 1 read-write 0 MPU is disabled. All accesses from all bus masters are allowed. #0 1 MPU is enabled #1 EAR0 Error Address Register, slave port n 0x20 32 read-only n 0x0 0x0 EADDR Error Address 0 32 read-only EAR1 Error Address Register, slave port n 0x38 32 read-only n 0x0 0x0 EADDR Error Address 0 32 read-only EAR2 Error Address Register, slave port n 0x58 32 read-only n 0x0 0x0 EADDR Error Address 0 32 read-only EAR3 Error Address Register, slave port n 0x80 32 read-only n 0x0 0x0 EADDR Error Address 0 32 read-only EAR4 Error Address Register, slave port n 0xB0 32 read-only n 0x0 0x0 EADDR Error Address 0 32 read-only EDR0 Error Detail Register, slave port n 0x28 32 read-only n 0x0 0x0 EACD Error Access Control Detail 16 16 read-only EATTR Error Attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error Master Number 4 4 read-only EPID Error Process Identification 8 8 read-only ERW Error Read/Write 0 1 read-only 0 Read #0 1 Write #1 EDR1 Error Detail Register, slave port n 0x44 32 read-only n 0x0 0x0 EACD Error Access Control Detail 16 16 read-only EATTR Error Attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error Master Number 4 4 read-only EPID Error Process Identification 8 8 read-only ERW Error Read/Write 0 1 read-only 0 Read #0 1 Write #1 EDR2 Error Detail Register, slave port n 0x68 32 read-only n 0x0 0x0 EACD Error Access Control Detail 16 16 read-only EATTR Error Attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error Master Number 4 4 read-only EPID Error Process Identification 8 8 read-only ERW Error Read/Write 0 1 read-only 0 Read #0 1 Write #1 EDR3 Error Detail Register, slave port n 0x94 32 read-only n 0x0 0x0 EACD Error Access Control Detail 16 16 read-only EATTR Error Attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error Master Number 4 4 read-only EPID Error Process Identification 8 8 read-only ERW Error Read/Write 0 1 read-only 0 Read #0 1 Write #1 EDR4 Error Detail Register, slave port n 0xC8 32 read-only n 0x0 0x0 EACD Error Access Control Detail 16 16 read-only EATTR Error Attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error Master Number 4 4 read-only EPID Error Process Identification 8 8 read-only ERW Error Read/Write 0 1 read-only 0 Read #0 1 Write #1 RGD0_WORD0 Region Descriptor n, Word 0 0x800 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write RGD0_WORD1 Region Descriptor n, Word 1 0x808 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write RGD0_WORD2 Region Descriptor n, Word 2 0x810 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD0_WORD3 Region Descriptor n, Word 3 0x818 32 read-write n 0x0 0x0 PID Process Identifier 24 8 read-write PIDMASK Process Identifier Mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD10_WORD0 Region Descriptor n, Word 0 0x3370 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write RGD10_WORD1 Region Descriptor n, Word 1 0x33A0 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write RGD10_WORD2 Region Descriptor n, Word 2 0x33D0 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD10_WORD3 Region Descriptor n, Word 3 0x3400 32 read-write n 0x0 0x0 PID Process Identifier 24 8 read-write PIDMASK Process Identifier Mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD11_WORD0 Region Descriptor n, Word 0 0x3820 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write RGD11_WORD1 Region Descriptor n, Word 1 0x3854 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write RGD11_WORD2 Region Descriptor n, Word 2 0x3888 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD11_WORD3 Region Descriptor n, Word 3 0x38BC 32 read-write n 0x0 0x0 PID Process Identifier 24 8 read-write PIDMASK Process Identifier Mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD1_WORD0 Region Descriptor n, Word 0 0xC10 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write RGD1_WORD1 Region Descriptor n, Word 1 0xC1C 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write RGD1_WORD2 Region Descriptor n, Word 2 0xC28 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD1_WORD3 Region Descriptor n, Word 3 0xC34 32 read-write n 0x0 0x0 PID Process Identifier 24 8 read-write PIDMASK Process Identifier Mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD2_WORD0 Region Descriptor n, Word 0 0x1030 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write RGD2_WORD1 Region Descriptor n, Word 1 0x1040 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write RGD2_WORD2 Region Descriptor n, Word 2 0x1050 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD2_WORD3 Region Descriptor n, Word 3 0x1060 32 read-write n 0x0 0x0 PID Process Identifier 24 8 read-write PIDMASK Process Identifier Mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD3_WORD0 Region Descriptor n, Word 0 0x1460 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write RGD3_WORD1 Region Descriptor n, Word 1 0x1474 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write RGD3_WORD2 Region Descriptor n, Word 2 0x1488 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD3_WORD3 Region Descriptor n, Word 3 0x149C 32 read-write n 0x0 0x0 PID Process Identifier 24 8 read-write PIDMASK Process Identifier Mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD4_WORD0 Region Descriptor n, Word 0 0x18A0 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write RGD4_WORD1 Region Descriptor n, Word 1 0x18B8 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write RGD4_WORD2 Region Descriptor n, Word 2 0x18D0 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD4_WORD3 Region Descriptor n, Word 3 0x18E8 32 read-write n 0x0 0x0 PID Process Identifier 24 8 read-write PIDMASK Process Identifier Mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD5_WORD0 Region Descriptor n, Word 0 0x1CF0 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write RGD5_WORD1 Region Descriptor n, Word 1 0x1D0C 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write RGD5_WORD2 Region Descriptor n, Word 2 0x1D28 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD5_WORD3 Region Descriptor n, Word 3 0x1D44 32 read-write n 0x0 0x0 PID Process Identifier 24 8 read-write PIDMASK Process Identifier Mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD6_WORD0 Region Descriptor n, Word 0 0x2150 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write RGD6_WORD1 Region Descriptor n, Word 1 0x2170 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write RGD6_WORD2 Region Descriptor n, Word 2 0x2190 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD6_WORD3 Region Descriptor n, Word 3 0x21B0 32 read-write n 0x0 0x0 PID Process Identifier 24 8 read-write PIDMASK Process Identifier Mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD7_WORD0 Region Descriptor n, Word 0 0x25C0 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write RGD7_WORD1 Region Descriptor n, Word 1 0x25E4 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write RGD7_WORD2 Region Descriptor n, Word 2 0x2608 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD7_WORD3 Region Descriptor n, Word 3 0x262C 32 read-write n 0x0 0x0 PID Process Identifier 24 8 read-write PIDMASK Process Identifier Mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD8_WORD0 Region Descriptor n, Word 0 0x2A40 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write RGD8_WORD1 Region Descriptor n, Word 1 0x2A68 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write RGD8_WORD2 Region Descriptor n, Word 2 0x2A90 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD8_WORD3 Region Descriptor n, Word 3 0x2AB8 32 read-write n 0x0 0x0 PID Process Identifier 24 8 read-write PIDMASK Process Identifier Mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD9_WORD0 Region Descriptor n, Word 0 0x2ED0 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write RGD9_WORD1 Region Descriptor n, Word 1 0x2EFC 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write RGD9_WORD2 Region Descriptor n, Word 2 0x2F28 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD9_WORD3 Region Descriptor n, Word 3 0x2F54 32 read-write n 0x0 0x0 PID Process Identifier 24 8 read-write PIDMASK Process Identifier Mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGDAAC0 Region Descriptor Alternate Access Control n 0x1000 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC1 Region Descriptor Alternate Access Control n 0x1804 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC10 Region Descriptor Alternate Access Control n 0x60DC 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC11 Region Descriptor Alternate Access Control n 0x6908 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC2 Region Descriptor Alternate Access Control n 0x200C 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC3 Region Descriptor Alternate Access Control n 0x2818 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC4 Region Descriptor Alternate Access Control n 0x3028 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC5 Region Descriptor Alternate Access Control n 0x383C 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC6 Region Descriptor Alternate Access Control n 0x4054 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC7 Region Descriptor Alternate Access Control n 0x4870 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC8 Region Descriptor Alternate Access Control n 0x5090 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC9 Region Descriptor Alternate Access Control n 0x58B4 32 read-write n 0x0 0x0 M0PE Bus Master 0 Process Identifier Enable 5 1 read-write M0SM Bus Master 0 Supervisor Mode Access Control 3 2 read-write M0UM Bus Master 0 User Mode Access Control 0 3 read-write M1PE Bus Master 1 Process Identifier Enable 11 1 read-write M1SM Bus Master 1 Supervisor Mode Access Control 9 2 read-write M1UM Bus Master 1 User Mode Access Control 6 3 read-write M2PE Bus Master 2 Process Identifier Enable 17 1 read-write M2SM Bus Master 2 Supervisor Mode Access Control 15 2 read-write M2UM Bus Master 2 User Mode Access Control 12 3 read-write M3PE Bus Master 3 Process Identifier Enable 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus Master 3 Supervisor Mode Access Control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as User mode defined in M3UM #11 M3UM Bus Master 3 User Mode Access Control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #000 1 Allows the given access type to occur #001 M4RE Bus Master 4 Read Enable 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus Master 4 Write Enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus Master 5 Read Enable 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus Master 5 Write Enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus Master 6 Read Enable 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus Master 6 Write Enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus Master 7 Read Enable 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus Master 7 Write Enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 MSCM MSCM MSCM 0x0 0x0 0x40C registers n CP0CFG1 Processor 0 Configuration 1 Register 0x34 32 read-only n 0x0 0x0 L2SZ Level 2 Cache Size 24 8 read-only L2WY Level 2 Cache Ways 16 8 read-only CP0CFG3 Processor 0 Configuration 3 Register 0x3C 32 read-only n 0x0 0x0 BB Bit Banding 6 1 read-only CMP Core Memory Protection unit 5 1 read-only FPU Floating Point Unit 0 1 read-only JAZ Jazelle 2 1 read-only MMU Memory Management Unit 3 1 read-only SBP System Bus Ports 8 2 read-only SIMD SIMD/NEON Instruction Support 1 1 read-only TZ Trust Zone 4 1 read-only CP0COUNT Processor 0 Count Register 0x2C 32 read-only n 0x0 0x0 PCNT Processor Count 0 2 read-only CP0MASTER Processor 0 Master Register 0x28 32 read-only n 0x0 0x0 PPN Processor 0 Physical Port Number 0 6 read-only CP0NUM Processor 0 Number Register 0x24 32 read-only n 0x0 0x0 CPN Processor 0 Number 0 1 read-only CP0TYPE Processor 0 Type Register 0x20 32 read-only n 0x0 0x0 PERSONALITY Processor 0 Personality 8 24 read-only RYPZ Processor 0 Revision 0 8 read-only CP1CFG1 Processor 1 Configuration 1 Register 0x54 32 read-only n 0x0 0x0 L2SZ Level 2 Cache Size 24 8 read-only L2WY Level 2 Cache Ways 16 8 read-only CP1CFG3 Processor 1 Configuration 3 Register 0x5C 32 read-only n 0x0 0x0 BB Bit Banding 6 1 read-only CMP Core Memory Protection unit 5 1 read-only FPU Floating Point Unit 0 1 read-only JAZ Jazelle 2 1 read-only MMU Memory Management Unit 3 1 read-only SBP System Bus Ports 8 2 read-only SIMD SIMD/NEON Instruction Support 1 1 read-only TZ Trust Zone 4 1 read-only CP1COUNT Processor 1 Count Register 0x4C 32 read-only n 0x0 0x0 PCNT Processor Count 0 2 read-only CP1MASTER Processor 1 Master Register 0x48 32 read-only n 0x0 0x0 PPN Processor 1 Physical Port Number 0 6 read-only CP1NUM Processor 1 Number Register 0x44 32 read-only n 0x0 0x0 CPN Processor 1 Number 0 1 read-only CP1TYPE Processor 1 Type Register 0x40 32 read-only n 0x0 0x0 PERSONALITY Processor 1 Personality 8 24 read-only RYPZ Processor 1 Revision 0 8 read-only CPxCFG1 Processor X Configuration 1 Register 0x14 32 read-only n 0x0 0x0 L2SZ Level 2 Cache Size 24 8 read-only L2WY Level 2 Cache Ways 16 8 read-only CPxCFG3 Processor X Configuration 3 Register 0x1C 32 read-only n 0x0 0x0 BB Bit Banding 6 1 read-only CMP Core Memory Protection unit 5 1 read-only FPU Floating Point Unit 0 1 read-only JAZ Jazelle 2 1 read-only MMU Memory Management Unit 3 1 read-only SBP System Bus Ports 8 2 read-only SIMD SIMD/NEON Instruction Support 1 1 read-only TZ Trust Zone 4 1 read-only CPxCOUNT Processor X Count Register 0xC 32 read-only n 0x0 0x0 PCNT Processor Count 0 2 read-only CPxMASTER Processor X Master Register 0x8 32 read-only n 0x0 0x0 PPN Processor x Physical Port Number 0 6 read-only CPxNUM Processor X Number Register 0x4 32 read-only n 0x0 0x0 CPN Processor x Number 0 1 read-only CPxTYPE Processor X Type Register 0x0 32 read-only n 0x0 0x0 PERSONALITY Processor x Personality 8 24 read-only RYPZ Processor x Revision 0 8 read-only OCMDR0 On-Chip Memory Descriptor Register 0x800 32 read-only n 0x0 0x0 FMT Format 30 1 read-only 0 Local #0 1 Global #1 OCMPU OCMEM Memory Protection Unit 12 1 read-only 0 OCMEMn is not protected by an MPU. #0 1 OCMEMn is protected by an MPU. #1 OCMSZ OCMEM Size 24 4 read-only 0000 no OCMEMn #0000 0011 4KB OCMEMn #0011 0100 8KB OCMEMn #0100 0101 16KB OCMEMn #0101 0110 32KB OCMEMn #0110 0111 64KB OCMEMn #0111 1000 128KB OCMEMn #1000 1001 256KB OCMEMn #1001 1010 512KB OCMEMn #1010 1011 1024KB OCMEMn #1011 1100 2048KB OCMEMn #1100 1101 4096KB OCMEMn #1101 1110 8192KB OCMEMn #1110 1111 16384KB OCMEMn #1111 OCMSZH OCMEM Size "Hole" 28 1 read-only 0 OCMEMn is a power-of-2 capacity. #0 1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. #1 OCMT OCMEM Type. This field defines the type of the on-chip memory: 13 3 read-only 000 OCMEMn is a system RAM. #000 001 OCMEMn is a graphics RAM. #001 011 OCMEMn is a ROM. #011 100 OCMEMn is a program flash. #100 101 OCMEMn is a data flash. #101 110 OCMEMn is an EEE. #110 OCMW OCMEM Datapath Width 17 3 read-only 010 OCMEMn 32-bits wide #010 011 OCMEMn 64-bits wide #011 100 OCMEMn 128-bits wide #100 101 OCMEMn 256-bits wide #101 V OCMEM Valid Bit 31 1 read-only 0 OCMEMn is not present. #0 1 OCMEMn is present. #1 OCMDR1 On-Chip Memory Descriptor Register 0xC04 32 read-only n 0x0 0x0 FMT Format 30 1 read-only 0 Local #0 1 Global #1 OCMPU OCMEM Memory Protection Unit 12 1 read-only 0 OCMEMn is not protected by an MPU. #0 1 OCMEMn is protected by an MPU. #1 OCMSZ OCMEM Size 24 4 read-only 0000 no OCMEMn #0000 0011 4KB OCMEMn #0011 0100 8KB OCMEMn #0100 0101 16KB OCMEMn #0101 0110 32KB OCMEMn #0110 0111 64KB OCMEMn #0111 1000 128KB OCMEMn #1000 1001 256KB OCMEMn #1001 1010 512KB OCMEMn #1010 1011 1024KB OCMEMn #1011 1100 2048KB OCMEMn #1100 1101 4096KB OCMEMn #1101 1110 8192KB OCMEMn #1110 1111 16384KB OCMEMn #1111 OCMSZH OCMEM Size "Hole" 28 1 read-only 0 OCMEMn is a power-of-2 capacity. #0 1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. #1 OCMT OCMEM Type. This field defines the type of the on-chip memory: 13 3 read-only 000 OCMEMn is a system RAM. #000 001 OCMEMn is a graphics RAM. #001 011 OCMEMn is a ROM. #011 100 OCMEMn is a program flash. #100 101 OCMEMn is a data flash. #101 110 OCMEMn is an EEE. #110 OCMW OCMEM Datapath Width 17 3 read-only 010 OCMEMn 32-bits wide #010 011 OCMEMn 64-bits wide #011 100 OCMEMn 128-bits wide #100 101 OCMEMn 256-bits wide #101 V OCMEM Valid Bit 31 1 read-only 0 OCMEMn is not present. #0 1 OCMEMn is present. #1 OCMDR2 On-Chip Memory Descriptor Register 0x100C 32 read-only n 0x0 0x0 FMT Format 30 1 read-only 0 Local #0 1 Global #1 OCMPU OCMEM Memory Protection Unit 12 1 read-only 0 OCMEMn is not protected by an MPU. #0 1 OCMEMn is protected by an MPU. #1 OCMSZ OCMEM Size 24 4 read-only 0000 no OCMEMn #0000 0011 4KB OCMEMn #0011 0100 8KB OCMEMn #0100 0101 16KB OCMEMn #0101 0110 32KB OCMEMn #0110 0111 64KB OCMEMn #0111 1000 128KB OCMEMn #1000 1001 256KB OCMEMn #1001 1010 512KB OCMEMn #1010 1011 1024KB OCMEMn #1011 1100 2048KB OCMEMn #1100 1101 4096KB OCMEMn #1101 1110 8192KB OCMEMn #1110 1111 16384KB OCMEMn #1111 OCMSZH OCMEM Size "Hole" 28 1 read-only 0 OCMEMn is a power-of-2 capacity. #0 1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. #1 OCMT OCMEM Type. This field defines the type of the on-chip memory: 13 3 read-only 000 OCMEMn is a system RAM. #000 001 OCMEMn is a graphics RAM. #001 011 OCMEMn is a ROM. #011 100 OCMEMn is a program flash. #100 101 OCMEMn is a data flash. #101 110 OCMEMn is an EEE. #110 OCMW OCMEM Datapath Width 17 3 read-only 010 OCMEMn 32-bits wide #010 011 OCMEMn 64-bits wide #011 100 OCMEMn 128-bits wide #100 101 OCMEMn 256-bits wide #101 V OCMEM Valid Bit 31 1 read-only 0 OCMEMn is not present. #0 1 OCMEMn is present. #1 OSC0 Oscillator OSC0 0x0 0x0 0x3 registers n CR OSC Control Register 0x0 8 read-write n 0x0 0x0 ERCLKEN External Reference Enable 7 1 read-write 0 External reference clock is inactive. #0 1 External reference clock is enabled. #1 EREFSTEN External Reference Stop Enable 5 1 read-write 0 External reference clock is disabled in Stop mode. #0 1 External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. #1 SC16P Oscillator 16 pF Capacitor Load Configure 0 1 read-write 0 Disable the selection. #0 1 Add 16 pF capacitor to the oscillator load. #1 SC2P Oscillator 2 pF Capacitor Load Configure 3 1 read-write 0 Disable the selection. #0 1 Add 2 pF capacitor to the oscillator load. #1 SC4P Oscillator 4 pF Capacitor Load Configure 2 1 read-write 0 Disable the selection. #0 1 Add 4 pF capacitor to the oscillator load. #1 SC8P Oscillator 8 pF Capacitor Load Configure 1 1 read-write 0 Disable the selection. #0 1 Add 8 pF capacitor to the oscillator load. #1 OSC_DIV OSC_DIV 0x2 8 read-write n 0x0 0x0 ERPS ERCLK prescaler 6 2 read-write 00 The divisor ratio is 1. #00 01 The divisor ratio is 2. #01 10 The divisor ratio is 4. #10 11 The divisor ratio is 8. #11 PDB0 Programmable Delay Block PDB 0x0 0x0 0x19C registers n PDB0 52 CH0C1 Channel n Control register 1 0x20 32 read-write n 0x0 0x0 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 CH0DLY0 Channel n Delay 0 register 0x30 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write CH0DLY1 Channel n Delay 1 register 0x38 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write CH0S Channel n Status register 0x28 32 read-write n 0x0 0x0 CF PDB Channel Flags 16 8 read-write ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. #1 CH1C1 Channel n Control register 1 0x58 32 read-write n 0x0 0x0 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 CH1DLY0 Channel n Delay 0 register 0x70 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write CH1DLY1 Channel n Delay 1 register 0x7C 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write CH1S Channel n Status register 0x64 32 read-write n 0x0 0x0 CF PDB Channel Flags 16 8 read-write ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. #1 CNT Counter register 0x8 32 read-only n 0x0 0x0 CNT PDB Counter 0 16 read-only DACINT DAC Interval n register 0x154 32 read-write n 0x0 0x0 INT DAC Interval 0 16 read-write DACINTC DAC Interval Trigger n Control register 0x150 32 read-write n 0x0 0x0 EXT DAC External Trigger Input Enable 1 1 read-write 0 DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. #1 TOE DAC Interval Trigger Enable 0 1 read-write 0 DAC interval trigger disabled. #0 1 DAC interval trigger enabled. #1 IDLY Interrupt Delay register 0xC 32 read-write n 0x0 0x0 IDLY PDB Interrupt Delay 0 16 read-write MOD Modulus register 0x4 32 read-write n 0x0 0x0 MOD PDB Modulus 0 16 read-write PO0DLY Pulse-Out n Delay register 0x328 32 read-write n 0x0 0x0 DLY1 PDB Pulse-Out Delay 1 16 16 read-write DLY2 PDB Pulse-Out Delay 2 0 16 read-write PO1DLY Pulse-Out n Delay register 0x4C0 32 read-write n 0x0 0x0 DLY1 PDB Pulse-Out Delay 1 16 16 read-write DLY2 PDB Pulse-Out Delay 2 0 16 read-write POEN Pulse-Out n Enable register 0x190 32 read-write n 0x0 0x0 POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 SC Status and Control register 0x0 32 read-write n 0x0 0x0 CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 DMAEN DMA Enable 15 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. #11 LDOK Load OK 0 1 read-write MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1. #00 01 Multiplication factor is 10. #01 10 Multiplication factor is 20. #10 11 Multiplication factor is 40. #11 PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled. #1 PDBIE PDB Interrupt Enable 5 1 read-write 0 PDB interrupt disabled. #0 1 PDB interrupt enabled. #1 PDBIF PDB Interrupt Flag 6 1 read-write PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by multiplication factor selected by MULT. #000 001 Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. #001 010 Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. #010 011 Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. #011 100 Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. #100 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. #101 110 Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. #110 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. #111 SWTRIG Software Trigger 16 1 write-only TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected. #0000 0001 Trigger-In 1 is selected. #0001 0010 Trigger-In 2 is selected. #0010 0011 Trigger-In 3 is selected. #0011 0100 Trigger-In 4 is selected. #0100 0101 Trigger-In 5 is selected. #0101 0110 Trigger-In 6 is selected. #0110 0111 Trigger-In 7 is selected. #0111 1000 Trigger-In 8 is selected. #1000 1001 Trigger-In 9 is selected. #1001 1010 Trigger-In 10 is selected. #1010 1011 Trigger-In 11 is selected. #1011 1100 Trigger-In 12 is selected. #1100 1101 Trigger-In 13 is selected. #1101 1110 Trigger-In 14 is selected. #1110 1111 Software trigger is selected. #1111 PDB1 Programmable Delay Block PDB 0x0 0x0 0x19C registers n PDB1 55 CH0C1 Channel n Control register 1 0x20 32 read-write n 0x0 0x0 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 CH0DLY0 Channel n Delay 0 register 0x30 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write CH0DLY1 Channel n Delay 1 register 0x38 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write CH0S Channel n Status register 0x28 32 read-write n 0x0 0x0 CF PDB Channel Flags 16 8 read-write ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. #1 CH1C1 Channel n Control register 1 0x58 32 read-write n 0x0 0x0 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 CH1DLY0 Channel n Delay 0 register 0x70 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write CH1DLY1 Channel n Delay 1 register 0x7C 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write CH1S Channel n Status register 0x64 32 read-write n 0x0 0x0 CF PDB Channel Flags 16 8 read-write ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. #1 CNT Counter register 0x8 32 read-only n 0x0 0x0 CNT PDB Counter 0 16 read-only DACINT DAC Interval n register 0x154 32 read-write n 0x0 0x0 INT DAC Interval 0 16 read-write DACINTC DAC Interval Trigger n Control register 0x150 32 read-write n 0x0 0x0 EXT DAC External Trigger Input Enable 1 1 read-write 0 DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. #1 TOE DAC Interval Trigger Enable 0 1 read-write 0 DAC interval trigger disabled. #0 1 DAC interval trigger enabled. #1 IDLY Interrupt Delay register 0xC 32 read-write n 0x0 0x0 IDLY PDB Interrupt Delay 0 16 read-write MOD Modulus register 0x4 32 read-write n 0x0 0x0 MOD PDB Modulus 0 16 read-write PO0DLY Pulse-Out n Delay register 0x328 32 read-write n 0x0 0x0 DLY1 PDB Pulse-Out Delay 1 16 16 read-write DLY2 PDB Pulse-Out Delay 2 0 16 read-write PO1DLY Pulse-Out n Delay register 0x4C0 32 read-write n 0x0 0x0 DLY1 PDB Pulse-Out Delay 1 16 16 read-write DLY2 PDB Pulse-Out Delay 2 0 16 read-write POEN Pulse-Out n Enable register 0x190 32 read-write n 0x0 0x0 POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 SC Status and Control register 0x0 32 read-write n 0x0 0x0 CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 DMAEN DMA Enable 15 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. #11 LDOK Load OK 0 1 read-write MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1. #00 01 Multiplication factor is 10. #01 10 Multiplication factor is 20. #10 11 Multiplication factor is 40. #11 PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled. #1 PDBIE PDB Interrupt Enable 5 1 read-write 0 PDB interrupt disabled. #0 1 PDB interrupt enabled. #1 PDBIF PDB Interrupt Flag 6 1 read-write PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by multiplication factor selected by MULT. #000 001 Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. #001 010 Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. #010 011 Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. #011 100 Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. #100 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. #101 110 Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. #110 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. #111 SWTRIG Software Trigger 16 1 write-only TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected. #0000 0001 Trigger-In 1 is selected. #0001 0010 Trigger-In 2 is selected. #0010 0011 Trigger-In 3 is selected. #0011 0100 Trigger-In 4 is selected. #0100 0101 Trigger-In 5 is selected. #0101 0110 Trigger-In 6 is selected. #0110 0111 Trigger-In 7 is selected. #0111 1000 Trigger-In 8 is selected. #1000 1001 Trigger-In 9 is selected. #1001 1010 Trigger-In 10 is selected. #1010 1011 Trigger-In 11 is selected. #1011 1100 Trigger-In 12 is selected. #1100 1101 Trigger-In 13 is selected. #1101 1110 Trigger-In 14 is selected. #1110 1111 Software trigger is selected. #1111 PIT Periodic Interrupt Timer PIT 0x0 0x0 0x140 registers n PIT0 48 PIT1 49 PIT2 50 PIT3 51 CVAL0 Current Timer Value Register 0x208 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only CVAL1 Current Timer Value Register 0x31C 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only CVAL2 Current Timer Value Register 0x440 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only CVAL3 Current Timer Value Register 0x574 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only LDVAL0 Timer Load Value Register 0x200 32 read-write n 0x0 0x0 TSV Timer Start Value 0 32 read-write LDVAL1 Timer Load Value Register 0x310 32 read-write n 0x0 0x0 TSV Timer Start Value 0 32 read-write LDVAL2 Timer Load Value Register 0x430 32 read-write n 0x0 0x0 TSV Timer Start Value 0 32 read-write LDVAL3 Timer Load Value Register 0x560 32 read-write n 0x0 0x0 TSV Timer Start Value 0 32 read-write LTMR64H PIT Upper Lifetime Timer Register 0xE0 32 read-only n 0x0 0x0 LTH Life Timer value 0 32 read-only LTMR64L PIT Lower Lifetime Timer Register 0xE4 32 read-only n 0x0 0x0 LTL Life Timer value 0 32 read-only MCR PIT Module Control Register 0x0 32 read-write n 0x0 0x0 FRZ Freeze 0 1 read-write 0 Timers continue to run in Debug mode. #0 1 Timers are stopped in Debug mode. #1 MDIS Module Disable - (PIT section) 1 1 read-write 0 Clock for standard PIT timers is enabled. #0 1 Clock for standard PIT timers is disabled. #1 TCTRL0 Timer Control Register 0x210 32 read-write n 0x0 0x0 CHN Chain Mode 2 1 read-write 0 Timer is not chained. #0 1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. #1 TEN Timer Enable 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is enabled. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TCTRL1 Timer Control Register 0x328 32 read-write n 0x0 0x0 CHN Chain Mode 2 1 read-write 0 Timer is not chained. #0 1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. #1 TEN Timer Enable 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is enabled. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TCTRL2 Timer Control Register 0x450 32 read-write n 0x0 0x0 CHN Chain Mode 2 1 read-write 0 Timer is not chained. #0 1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. #1 TEN Timer Enable 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is enabled. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TCTRL3 Timer Control Register 0x588 32 read-write n 0x0 0x0 CHN Chain Mode 2 1 read-write 0 Timer is not chained. #0 1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. #1 TEN Timer Enable 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is enabled. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TFLG0 Timer Flag Register 0x218 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TFLG1 Timer Flag Register 0x334 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TFLG2 Timer Flag Register 0x460 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TFLG3 Timer Flag Register 0x59C 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 PMC Power Management Controller PMC 0x0 0x0 0xC registers n PMC 20 HVDSC1 High Voltage Detect Status And Control 1 register 0xB 8 read-write n 0x0 0x0 HVDACK High-Voltage Detect Acknowledge 6 1 write-only HVDF High-Voltage Detect Flag 7 1 read-only 0 High-voltage event not detected #0 1 High-voltage event detected #1 HVDIE High-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when HVDF = 1 #1 HVDRE High-Voltage Detect Reset Enable 4 1 read-write 0 HVDF does not generate hardware resets #0 1 Force an MCU reset when HVDF = 1 #1 HVDV High-Voltage Detect Voltage Select 0 1 read-write 0 Low trip point selected (V HVD = V HVDL ) #0 1 High trip point selected (V HVD = V HVDH ) #1 LVDSC1 Low Voltage Detect Status And Control 1 register 0x0 8 read-write n 0x0 0x0 LVDACK Low-Voltage Detect Acknowledge 6 1 write-only LVDF Low-Voltage Detect Flag 7 1 read-only 0 Low-voltage event not detected #0 1 Low-voltage event detected #1 LVDIE Low-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVDF = 1 #1 LVDRE Low-Voltage Detect Reset Enable 4 1 read-write 0 LVDF does not generate hardware resets #0 1 Force an MCU reset when LVDF = 1 #1 LVDV Low-Voltage Detect Voltage Select 0 2 read-write 00 Low trip point selected (V LVD = V LVDL ) #00 01 High trip point selected (V LVD = V LVDH ) #01 LVDSC2 Low Voltage Detect Status And Control 2 register 0x1 8 read-write n 0x0 0x0 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning event not detected #0 1 Low-voltage warning event detected #1 LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVWF = 1 #1 LVWV Low-Voltage Warning Voltage Select 0 2 read-write 00 Low trip point selected (VLVW = VLVW1) #00 01 Mid 1 trip point selected (VLVW = VLVW2) #01 10 Mid 2 trip point selected (VLVW = VLVW3) #10 11 High trip point selected (VLVW = VLVW4) #11 REGSC Regulator Status And Control register 0x2 8 read-write n 0x0 0x0 ACKISO Acknowledge Isolation 3 1 read-write 0 Peripherals and I/O pads are in normal run state. #0 1 Certain peripherals and I/O pads are in an isolated and latched state. #1 BGBE Bandgap Buffer Enable 0 1 read-write 0 Bandgap buffer not enabled #0 1 Bandgap buffer enabled #1 BGEN Bandgap Enable In VLPx Operation 4 1 read-write 0 Bandgap voltage reference is disabled in VLPx , and VLLSx modes. #0 1 Bandgap voltage reference is enabled in VLPx , and VLLSx modes. #1 REGONS Regulator In Run Regulation Status 2 1 read-only 0 Regulator is in stop regulation or in transition to/from it #0 1 Regulator is in run regulation #1 PORTA Pin Control and Interrupts PORT 0x0 0x0 0xA4 registers n PORTA 59 GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR10 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x30 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x34 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x38 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x40 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x44 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x48 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x4C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register n 0x8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x50 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x58 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x5C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x60 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x64 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x68 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x6C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x74 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR3 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x78 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x10 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x14 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x1C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x20 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR9 Pin Control Register n 0x24 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PORTB Pin Control and Interrupts PORT 0x0 0x0 0xA4 registers n PORTB 60 GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR10 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x30 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x34 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x38 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x40 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x44 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x48 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x4C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register n 0x8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x50 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x58 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x5C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x60 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x64 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x68 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x6C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x74 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR3 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x78 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x10 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x14 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x1C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x20 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR9 Pin Control Register n 0x24 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PORTC Pin Control and Interrupts PORT 0x0 0x0 0xA4 registers n PORTC 61 GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR10 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x30 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x34 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x38 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x40 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x44 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x48 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x4C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register n 0x8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x50 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x58 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x5C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x60 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x64 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x68 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x6C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x74 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR3 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x78 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x10 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x14 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x1C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x20 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR9 Pin Control Register n 0x24 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PORTD Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTD 62 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR10 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x30 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x34 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x38 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x40 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x44 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x48 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x4C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register n 0x8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x50 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x58 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x5C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x60 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x64 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x68 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x6C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x74 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR3 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x78 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x10 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x14 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x1C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x20 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR9 Pin Control Register n 0x24 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PORTE Pin Control and Interrupts PORT 0x0 0x0 0xA4 registers n PORTE 63 GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR10 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x30 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x34 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x38 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x40 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x44 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x48 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x4C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register n 0x8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x50 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x58 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x5C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x60 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x64 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x68 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x6C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x74 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR3 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x78 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x10 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x14 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x1C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x20 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR9 Pin Control Register n 0x24 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 LK Lock Register 15 1 read-write 0 Pin Control Register fields [15:0] are not locked. #0 1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. #1 MUX Pin Mux Control 8 4 read-write 000 Pin disabled (Alternative 0) (analog). #0000 001 Alternative 1 (GPIO). #0001 010 Alternative 2 (chip-specific). #0010 011 Alternative 3 (chip-specific). #0011 100 Alternative 4 (chip-specific). #0100 101 Alternative 5 (chip-specific). #0101 110 Alternative 6 (chip-specific). #0110 111 Alternative 7 (chip-specific). #0111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PWM0 Pulse Width Modulator with nano edge placement PWM 0x0 0x0 0x196 registers n PWM0_CMP0 81 PWM0_RELOAD0 82 PWM0_CMP1 83 PWM0_RELOAD1 84 PWM0_CMP2 85 PWM0_RELOAD2 86 PWM0_CMP3 87 PWM0_RELOAD3 88 PWM0_CAP 89 PWM0_RERR 90 PWM0_FAULT 91 DTSRCSEL PWM Source Select Register 0x186 16 read-write n 0x0 0x0 SM0SEL23 Submodule 0 PWM23 Control Select 2 2 read-write 00 Generated SM0PWM23 signal is used by the deadtime logic. #00 01 Inverted generated SM0PWM23 signal is used by the deadtime logic. #01 10 SWCOUT[SM0OUT23] is used by the deadtime logic. #10 11 PWMx_EXTA0 signal is used by the deadtime logic. #11 SM0SEL45 Submodule 0 PWM45 Control Select 0 2 read-write 00 Generated SM0PWM45 signal is used by the deadtime logic. #00 01 Inverted generated SM0PWM45 signal is used by the deadtime logic. #01 10 SWCOUT[SM0OUT45] is used by the deadtime logic. #10 11 PWMx_EXTB0 signal is used by the deadtime logic. #11 SM1SEL23 Submodule 1 PWM23 Control Select 6 2 read-write 00 Generated SM1PWM23 signal is used by the deadtime logic. #00 01 Inverted generated SM1PWM23 signal is used by the deadtime logic. #01 10 SWCOUT[SM1OUT23] is used by the deadtime logic. #10 11 PWMx_EXTA1 signal is used by the deadtime logic. #11 SM1SEL45 Submodule 1 PWM45 Control Select 4 2 read-write 00 Generated SM1PWM45 signal is used by the deadtime logic. #00 01 Inverted generated SM1PWM45 signal is used by the deadtime logic. #01 10 SWCOUT[SM1OUT45] is used by the deadtime logic. #10 11 PWMx_EXTB1 signal is used by the deadtime logic. #11 SM2SEL23 Submodule 2 PWM23 Control Select 10 2 read-write 00 Generated SM2PWM23 signal is used by the deadtime logic. #00 01 Inverted generated SM2PWM23 signal is used by the deadtime logic. #01 10 SWCOUT[SM2OUT23] is used by the deadtime logic. #10 11 PWMx_EXTA2 signal is used by the deadtime logic. #11 SM2SEL45 Submodule 2 PWM45 Control Select 8 2 read-write 00 Generated SM2PWM45 signal is used by the deadtime logic. #00 01 Inverted generated SM2PWM45 signal is used by the deadtime logic. #01 10 SWCOUT[SM2OUT45] is used by the deadtime logic. #10 11 PWMx_EXTB2 signal is used by the deadtime logic. #11 SM3SEL23 Submodule 3 PWM23 Control Select 14 2 read-write 00 Generated SM3PWM23 signal is used by the deadtime logic. #00 01 Inverted generated SM3PWM23 signal is used by the deadtime logic. #01 10 SWCOUT[SM3OUT23] is used by the deadtime logic. #10 11 PWMx_EXTA3 signal is used by the deadtime logic. #11 SM3SEL45 Submodule 3 PWM45 Control Select 12 2 read-write 00 Generated SM3PWM45 signal is used by the deadtime logic. #00 01 Inverted generated SM3PWM45 signal is used by the deadtime logic. #01 10 SWCOUT[SM3OUT45] is used by the deadtime logic. #10 11 PWMx_EXTB3 signal is used by the deadtime logic. #11 FCTRL Fault Control Register 0x18C 16 read-write n 0x0 0x0 FAUTO Automatic Fault Clearing 8 4 read-write 0 Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further controlled by FCTRL[FSAFE]. #0000 1 Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. #0001 FIE Fault Interrupt Enables 0 4 read-write 0 FAULTx CPU interrupt requests disabled. #0000 1 FAULTx CPU interrupt requests enabled. #0001 FLVL Fault Level 12 4 read-write 0 A logic 0 on the fault input indicates a fault condition. #0000 1 A logic 1 on the fault input indicates a fault condition. #0001 FSAFE Fault Safety Mode 4 4 read-write 0 Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). #0000 1 Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL]. #0001 FCTRL2 Fault Control 2 Register 0x194 16 read-write n 0x0 0x0 NOCOMB No Combinational Path From Fault Input To PWM Output 0 4 read-write 0 There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. #0000 1 The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs. #0001 FFILT Fault Filter Register 0x190 16 read-write n 0x0 0x0 FILT_CNT Fault Filter Count 8 3 read-write FILT_PER Fault Filter Period 0 8 read-write GSTR Fault Glitch Stretch Enable 15 1 read-write 0 Fault input glitch stretching is disabled. #0 1 Input fault signals will be stretched to at least 2 IPBus clock cycles. #1 FSTS Fault Status Register 0x18E 16 read-write n 0x0 0x0 FFLAG Fault Flags 0 4 read-write 0 No fault on the FAULTx pin. #0000 1 Fault on the FAULTx pin. #0001 FFPIN Filtered Fault Pins 8 4 read-only FFULL Full Cycle 4 4 read-write 0 PWM outputs are not re-enabled at the start of a full cycle #0000 1 PWM outputs are re-enabled at the start of a full cycle #0001 FHALF Half Cycle Fault Recovery 12 4 read-write 0 PWM outputs are not re-enabled at the start of a half cycle. #0000 1 PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). #0001 FTST Fault Test Register 0x192 16 read-write n 0x0 0x0 FTEST Fault Test 0 1 read-write 0 No fault #0 1 Cause a simulated fault #1 MASK Mask Register 0x182 16 read-write n 0x0 0x0 MASKA PWM_A Masks 8 4 read-write 0 PWM_A output normal. #0000 1 PWM_A output masked. #0001 MASKB PWM_B Masks 4 4 read-write 0 PWM_B output normal. #0000 1 PWM_B output masked. #0001 MASKX PWM_X Masks 0 4 read-write 0 PWM_X output normal. #0000 1 PWM_X output masked. #0001 UPDATE_MASK Update Mask Bits Immediately 12 4 write-only 0 Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. #0000 1 Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. #0001 MCTRL0 Master Control Register 0 0x188 16 read-write n 0x0 0x0 CLDOK Clear Load Okay 4 4 write-only IPOL Current Polarity 12 4 read-write 0 PWM23 is used to generate complementary PWM pair in the corresponding submodule. #0000 1 PWM45 is used to generate complementary PWM pair in the corresponding submodule. #0001 LDOK Load Okay 0 4 read-write 0 Do not load new values. #0000 1 Load prescaler, modulus, and PWM values of the corresponding submodule. #0001 RUN Run 8 4 read-write 0 PWM generator is disabled in the corresponding submodule. #0000 1 PWM generator is enabled in the corresponding submodule. #0001 MCTRL1 Master Control Register 1 0x18A 16 read-write n 0x0 0x0 MONPLL Monitor PLL State 0 2 read-write 00 Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. #00 01 Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. #01 10 Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset. #10 11 Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset. #11 OUTEN Output Enable Register 0x180 16 read-write n 0x0 0x0 PWMA_EN PWM_A Output Enables 8 4 read-write 0 PWM_A output disabled. #0000 1 PWM_A output enabled. #0001 PWMB_EN PWM_B Output Enables 4 4 read-write 0 PWM_B output disabled. #0000 1 PWM_B output enabled. #0001 PWMX_EN PWM_X Output Enables 0 4 read-write 0 PWM_X output disabled. #0000 1 PWM_X output enabled. #0001 SM0CAPTCOMPA Capture Compare A Register 0x6C 16 read-write n 0x0 0x0 EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only SM0CAPTCOMPB Capture Compare B Register 0x74 16 read-write n 0x0 0x0 EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only SM0CAPTCOMPX Capture Compare X Register 0x7C 16 read-write n 0x0 0x0 EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only SM0CAPTCTRLA Capture Control A Register 0x68 16 read-write n 0x0 0x0 ARMA Arm A 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. #1 CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only CFAWM Capture A FIFOs Water Mark 8 2 read-write EDGA0 Edge A 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGA1 Edge A 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTA_EN Edge Counter A Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELA Input Select A 6 1 read-write 0 Raw PWM_A input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. #1 ONESHOTA One Shot Mode A 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. #1 SM0CAPTCTRLB Capture Control B Register 0x70 16 read-write n 0x0 0x0 ARMB Arm B 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. #1 CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only CFBWM Capture B FIFOs Water Mark 8 2 read-write EDGB0 Edge B 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGB1 Edge B 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTB_EN Edge Counter B Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELB Input Select B 6 1 read-write 0 Raw PWM_B input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. #1 ONESHOTB One Shot Mode B 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. #1 SM0CAPTCTRLX Capture Control X Register 0x78 16 read-write n 0x0 0x0 ARMX Arm X 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. #1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only EDGCNTX_EN Edge Counter X Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 EDGX0 Edge X 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGX1 Edge X 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 INP_SELX Input Select X 6 1 read-write 0 Raw PWM_X input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. #1 ONESHOTX One Shot Mode Aux 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. #1 SM0CNT Counter Register 0x0 16 read-only n 0x0 0x0 CNT Counter Register Bits 0 16 read-only SM0CTRL Control Register 0xC 16 read-write n 0x0 0x0 DBLEN Double Switching Enable 0 1 read-write 0 Double switching disabled. #0 1 Double switching enabled. #1 DBLX PWMX Double Switching Enable 1 1 read-write 0 PWMX double pulse disabled. #0 1 PWMX double pulse enabled. #1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write 0 Full-cycle reloads disabled. #0 1 Full-cycle reloads enabled. #1 HALF Half Cycle Reload 11 1 read-write 0 Half-cycle reloads disabled. #0 1 Half-cycle reloads enabled. #1 LDFQ Load Frequency 12 4 read-write 0000 Every PWM opportunity #0000 0001 Every 2 PWM opportunities #0001 0010 Every 3 PWM opportunities #0010 0011 Every 4 PWM opportunities #0011 0100 Every 5 PWM opportunities #0100 0101 Every 6 PWM opportunities #0101 0110 Every 7 PWM opportunities #0110 0111 Every 8 PWM opportunities #0111 1000 Every 9 PWM opportunities #1000 1001 Every 10 PWM opportunities #1001 1010 Every 11 PWM opportunities #1010 1011 Every 12 PWM opportunities #1011 1100 Every 13 PWM opportunities #1100 1101 Every 14 PWM opportunities #1101 1110 Every 15 PWM opportunities #1110 1111 Every 16 PWM opportunities #1111 LDMOD Load Mode Select 2 1 read-write 0 Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set. #0 1 Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. #1 PRSC Prescaler 4 3 read-write 000 PWM clock frequency = fclk #000 001 PWM clock frequency = fclk/2 #001 010 PWM clock frequency = fclk/4 #010 011 PWM clock frequency = fclk/8 #011 100 PWM clock frequency = fclk/16 #100 101 PWM clock frequency = fclk/32 #101 110 PWM clock frequency = fclk/64 #110 111 PWM clock frequency = fclk/128 #111 SM0CTRL2 Control 2 Register 0x8 16 read-write n 0x0 0x0 CLK_SEL Clock Source Select 0 2 read-write 00 The IPBus clock is used as the clock for the local prescaler and counter. #00 01 EXT_CLK is used as the clock for the local prescaler and counter. #01 10 Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. #10 DBGEN Debug Enable 15 1 read-write FORCE Force Initialization 6 1 write-only FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write 000 The local force signal, CTRL2[FORCE], from this submodule is used to force updates. #000 001 The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. #001 010 The local reload signal from this submodule is used to force updates without regard to the state of LDOK. #010 011 The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #011 100 The local sync signal from this submodule is used to force updates. #100 101 The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #101 110 The external force signal, EXT_FORCE, from outside the PWM module causes updates. #110 111 The external sync signal, EXT_SYNC, from outside the PWM module causes updates. #111 FRCEN This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by CTRL2[INIT_SEL] 7 1 read-write 0 Initialization from a FORCE_OUT is disabled. #0 1 Initialization from a FORCE_OUT is enabled. #1 INDEP Independent or Complementary Pair Operation 13 1 read-write 0 PWM_A and PWM_B form a complementary PWM pair. #0 1 PWM_A and PWM_B outputs are independent PWMs. #1 INIT_SEL Initialization Control Select 8 2 read-write 00 Local sync (PWM_X) causes initialization. #00 01 Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. #01 10 Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. #10 11 EXT_SYNC causes initialization. #11 PWM23_INIT PWM23 Initial Value 12 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWMX_INIT PWM_X Initial Value 10 1 read-write RELOAD_SEL Reload Source Select 2 1 read-write 0 The local RELOAD signal is used to reload registers. #0 1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. #1 WAITEN WAIT Enable 14 1 read-write SM0CVAL0 Capture Value 0 Register 0x80 16 read-only n 0x0 0x0 CAPTVAL0 This read-only register stores the value captured from the submodule counter 0 16 read-only SM0CVAL0CYC Capture Value 0 Cycle Register 0x84 16 read-only n 0x0 0x0 CVAL0CYC This read-only register stores the cycle number corresponding to the value captured in CVAL0 0 4 read-only SM0CVAL1 Capture Value 1 Register 0x88 16 read-only n 0x0 0x0 CAPTVAL1 This read-only register stores the value captured from the submodule counter 0 16 read-only SM0CVAL1CYC Capture Value 1 Cycle Register 0x8C 16 read-only n 0x0 0x0 CVAL1CYC This read-only register stores the cycle number corresponding to the value captured in CVAL1 0 4 read-only SM0CVAL2 Capture Value 2 Register 0x90 16 read-only n 0x0 0x0 CAPTVAL2 This read-only register stores the value captured from the submodule counter 0 16 read-only SM0CVAL2CYC Capture Value 2 Cycle Register 0x94 16 read-only n 0x0 0x0 CVAL2CYC This read-only register stores the cycle number corresponding to the value captured in CVAL2 0 4 read-only SM0CVAL3 Capture Value 3 Register 0x98 16 read-only n 0x0 0x0 CAPTVAL3 This read-only register stores the value captured from the submodule counter 0 16 read-only SM0CVAL3CYC Capture Value 3 Cycle Register 0x9C 16 read-only n 0x0 0x0 CVAL3CYC This read-only register stores the cycle number corresponding to the value captured in CVAL3 0 4 read-only SM0CVAL4 Capture Value 4 Register 0xA0 16 read-only n 0x0 0x0 CAPTVAL4 This read-only register stores the value captured from the submodule counter 0 16 read-only SM0CVAL4CYC Capture Value 4 Cycle Register 0xA4 16 read-only n 0x0 0x0 CVAL4CYC This read-only register stores the cycle number corresponding to the value captured in CVAL4 0 4 read-only SM0CVAL5 Capture Value 5 Register 0xA8 16 read-only n 0x0 0x0 CAPTVAL5 This read-only register stores the value captured from the submodule counter 0 16 read-only SM0CVAL5CYC Capture Value 5 Cycle Register 0xAC 16 read-only n 0x0 0x0 CVAL5CYC This read-only register stores the cycle number corresponding to the value captured in CVAL5 0 4 read-only SM0DISMAP0 Fault Disable Mapping Register 0 0x58 16 read-write n 0x0 0x0 DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write SM0DMAEN DMA Enable Register 0x50 16 read-write n 0x0 0x0 CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write 00 Read DMA requests disabled. #00 01 Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. #01 10 A local sync (VAL1 matches counter) sets the read DMA request. #10 11 A local reload (STS[RF] being set) sets the read DMA request. #11 CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write FAND FIFO Watermark AND Control 8 1 read-write 0 Selected FIFO watermarks are OR'ed together. #0 1 Selected FIFO watermarks are AND'ed together. #1 VALDE Value Registers DMA Enable 9 1 read-write 0 DMA write requests disabled #0 1 DMA write requests for the VALx and FRACVALx registers enabled #1 SM0DTCNT0 Deadtime Count Register 0 0x60 16 read-write n 0x0 0x0 DTCNT0 The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC23_EN] is set) 0 16 read-write SM0DTCNT1 Deadtime Count Register 1 0x64 16 read-write n 0x0 0x0 DTCNT1 The DTCNT1 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC45_EN] is set) 0 16 read-write SM0FRACVAL1 Fractional Value Register 1 0x18 16 read-write n 0x0 0x0 FRACVAL1 Fractional Value 1 Register 11 5 read-write SM0FRACVAL2 Fractional Value Register 2 0x20 16 read-write n 0x0 0x0 FRACVAL2 Fractional Value 2 11 5 read-write SM0FRACVAL3 Fractional Value Register 3 0x28 16 read-write n 0x0 0x0 FRACVAL3 Fractional Value 3 11 5 read-write SM0FRACVAL4 Fractional Value Register 4 0x30 16 read-write n 0x0 0x0 FRACVAL4 Fractional Value 4 11 5 read-write SM0FRACVAL5 Fractional Value Register 5 0x38 16 read-write n 0x0 0x0 FRACVAL5 Fractional Value 5 11 5 read-write SM0FRCTRL Fractional Control Register 0x40 16 read-write n 0x0 0x0 FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write 0 Disable fractional cycle length for the PWM period. #0 1 Enable fractional cycle length for the PWM period. #1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write 0 Disable fractional cycle placement for PWM_A. #0 1 Enable fractional cycle placement for PWM_A. #1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write 0 Disable fractional cycle placement for PWM_B. #0 1 Enable fractional cycle placement for PWM_B. #1 FRAC_PU Fractional Delay Circuit Power Up 8 1 read-write 0 Turn off fractional delay logic. #0 1 Power up fractional delay logic. #1 TEST Test Status Bit 15 1 read-only SM0INIT Initial Count Register 0x4 16 read-write n 0x0 0x0 INIT Initial Count Register Bits 0 16 read-write SM0INTEN Interrupt Enable Register 0x4C 16 read-write n 0x0 0x0 CA0IE Capture A 0 Interrupt Enable 10 1 read-write 0 Interrupt request disabled for STS[CFA0]. #0 1 Interrupt request enabled for STS[CFA0]. #1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write 0 Interrupt request disabled for STS[CFA1]. #0 1 Interrupt request enabled for STS[CFA1]. #1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write 0 Interrupt request disabled for STS[CFB0]. #0 1 Interrupt request enabled for STS[CFB0]. #1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write 0 Interrupt request disabled for STS[CFB1]. #0 1 Interrupt request enabled for STS[CFB1]. #1 CMPIE Compare Interrupt Enables 0 6 read-write 0 The corresponding STS[CMPF] bit will not cause an interrupt request. #0 1 The corresponding STS[CMPF] bit will cause an interrupt request. #1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write 0 Interrupt request disabled for STS[CFX0]. #0 1 Interrupt request enabled for STS[CFX0]. #1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write 0 Interrupt request disabled for STS[CFX1]. #0 1 Interrupt request enabled for STS[CFX1]. #1 REIE Reload Error Interrupt Enable 13 1 read-write 0 STS[REF] CPU interrupt requests disabled #0 1 STS[REF] CPU interrupt requests enabled #1 RIE Reload Interrupt Enable 12 1 read-write 0 STS[RF] CPU interrupt requests disabled #0 1 STS[RF] CPU interrupt requests enabled #1 SM0OCTRL Output Control Register 0x44 16 read-write n 0x0 0x0 POLA PWM_A Output Polarity 10 1 read-write 0 PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. #0 1 PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. #1 POLB PWM_B Output Polarity 9 1 read-write 0 PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. #0 1 PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. #1 POLX PWM_X Output Polarity 8 1 read-write 0 PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. #0 1 PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. #1 PWMAFS PWM_A Fault State 4 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMA_IN PWM_A Input 15 1 read-only PWMBFS PWM_B Fault State 2 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMB_IN PWM_B Input 14 1 read-only PWMXFS PWM_X Fault State 0 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMX_IN PWM_X Input 13 1 read-only SM0STS Status Register 0x48 16 read-write n 0x0 0x0 CFA0 Capture Flag A0 10 1 read-write CFA1 Capture Flag A1 11 1 read-write CFB0 Capture Flag B0 8 1 read-write CFB1 Capture Flag B1 9 1 read-write CFX0 Capture Flag X0 6 1 read-write CFX1 Capture Flag X1 7 1 read-write CMPF Compare Flags 0 6 read-write 0 No compare event has occurred for a particular VALx value. #0 1 A compare event has occurred for a particular VALx value. #1 REF Reload Error Flag 13 1 read-write 0 No reload error occurred. #0 1 Reload signal occurred with non-coherent data and MCTRL0[LDOK] = 0. #1 RF Reload Flag 12 1 read-write 0 No new reload cycle since last STS[RF] clearing #0 1 New reload cycle since last STS[RF] clearing #1 RUF Registers Updated Flag 14 1 read-only 0 No register update has occurred since last reload. #0 1 At least one of the double buffered registers has been updated since the last reload. #1 SM0TCTRL Output Trigger Control Register 0x54 16 read-write n 0x0 0x0 OUT_TRIG_EN Output Trigger Enables 0 6 read-write 0 PWM_OUT_TRIGx will not set when the counter value matches the VALx value. #0 1 PWM_OUT_TRIGx will set when the counter value matches the VALx value. #1 PWAOT0 Output Trigger 0 Source Select 15 1 read-write 0 Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. #0 1 Route the PWM0 output to the PWM_OUT_TRIG0 port. #1 PWBOT1 Output Trigger 1 Source Select 14 1 read-write 0 Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. #0 1 Route the PWM1 output to the PWM_OUT_TRIG1 port. #1 TRGFRQ Trigger frequency 12 1 read-write 0 Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #0 1 Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #1 SM0VAL0 Value Register 0 0x14 16 read-write n 0x0 0x0 VAL0 Value Register 0 0 16 read-write SM0VAL1 Value Register 1 0x1C 16 read-write n 0x0 0x0 VAL1 Value Register 1 0 16 read-write SM0VAL2 Value Register 2 0x24 16 read-write n 0x0 0x0 VAL2 Value Register 2 0 16 read-write SM0VAL3 Value Register 3 0x2C 16 read-write n 0x0 0x0 VAL3 Value Register 3 0 16 read-write SM0VAL4 Value Register 4 0x34 16 read-write n 0x0 0x0 VAL4 Value Register 4 0 16 read-write SM0VAL5 Value Register 5 0x3C 16 read-write n 0x0 0x0 VAL5 Value Register 5 0 16 read-write SM1CAPTCOMPA Capture Compare A Register 0x102 16 read-write n 0x0 0x0 EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only SM1CAPTCOMPB Capture Compare B Register 0x10E 16 read-write n 0x0 0x0 EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only SM1CAPTCOMPX Capture Compare X Register 0x11A 16 read-write n 0x0 0x0 EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only SM1CAPTCTRLA Capture Control A Register 0xFC 16 read-write n 0x0 0x0 ARMA Arm A 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. #1 CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only CFAWM Capture A FIFOs Water Mark 8 2 read-write EDGA0 Edge A 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGA1 Edge A 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTA_EN Edge Counter A Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELA Input Select A 6 1 read-write 0 Raw PWM_A input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. #1 ONESHOTA One Shot Mode A 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. #1 SM1CAPTCTRLB Capture Control B Register 0x108 16 read-write n 0x0 0x0 ARMB Arm B 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. #1 CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only CFBWM Capture B FIFOs Water Mark 8 2 read-write EDGB0 Edge B 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGB1 Edge B 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTB_EN Edge Counter B Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELB Input Select B 6 1 read-write 0 Raw PWM_B input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. #1 ONESHOTB One Shot Mode B 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. #1 SM1CAPTCTRLX Capture Control X Register 0x114 16 read-write n 0x0 0x0 ARMX Arm X 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. #1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only EDGCNTX_EN Edge Counter X Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 EDGX0 Edge X 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGX1 Edge X 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 INP_SELX Input Select X 6 1 read-write 0 Raw PWM_X input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. #1 ONESHOTX One Shot Mode Aux 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. #1 SM1CNT Counter Register 0x60 16 read-only n 0x0 0x0 CNT Counter Register Bits 0 16 read-only SM1CTRL Control Register 0x72 16 read-write n 0x0 0x0 DBLEN Double Switching Enable 0 1 read-write 0 Double switching disabled. #0 1 Double switching enabled. #1 DBLX PWMX Double Switching Enable 1 1 read-write 0 PWMX double pulse disabled. #0 1 PWMX double pulse enabled. #1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write 0 Full-cycle reloads disabled. #0 1 Full-cycle reloads enabled. #1 HALF Half Cycle Reload 11 1 read-write 0 Half-cycle reloads disabled. #0 1 Half-cycle reloads enabled. #1 LDFQ Load Frequency 12 4 read-write 0000 Every PWM opportunity #0000 0001 Every 2 PWM opportunities #0001 0010 Every 3 PWM opportunities #0010 0011 Every 4 PWM opportunities #0011 0100 Every 5 PWM opportunities #0100 0101 Every 6 PWM opportunities #0101 0110 Every 7 PWM opportunities #0110 0111 Every 8 PWM opportunities #0111 1000 Every 9 PWM opportunities #1000 1001 Every 10 PWM opportunities #1001 1010 Every 11 PWM opportunities #1010 1011 Every 12 PWM opportunities #1011 1100 Every 13 PWM opportunities #1100 1101 Every 14 PWM opportunities #1101 1110 Every 15 PWM opportunities #1110 1111 Every 16 PWM opportunities #1111 LDMOD Load Mode Select 2 1 read-write 0 Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set. #0 1 Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. #1 PRSC Prescaler 4 3 read-write 000 PWM clock frequency = fclk #000 001 PWM clock frequency = fclk/2 #001 010 PWM clock frequency = fclk/4 #010 011 PWM clock frequency = fclk/8 #011 100 PWM clock frequency = fclk/16 #100 101 PWM clock frequency = fclk/32 #101 110 PWM clock frequency = fclk/64 #110 111 PWM clock frequency = fclk/128 #111 SM1CTRL2 Control 2 Register 0x6C 16 read-write n 0x0 0x0 CLK_SEL Clock Source Select 0 2 read-write 00 The IPBus clock is used as the clock for the local prescaler and counter. #00 01 EXT_CLK is used as the clock for the local prescaler and counter. #01 10 Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. #10 DBGEN Debug Enable 15 1 read-write FORCE Force Initialization 6 1 write-only FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write 000 The local force signal, CTRL2[FORCE], from this submodule is used to force updates. #000 001 The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. #001 010 The local reload signal from this submodule is used to force updates without regard to the state of LDOK. #010 011 The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #011 100 The local sync signal from this submodule is used to force updates. #100 101 The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #101 110 The external force signal, EXT_FORCE, from outside the PWM module causes updates. #110 111 The external sync signal, EXT_SYNC, from outside the PWM module causes updates. #111 FRCEN This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by CTRL2[INIT_SEL] 7 1 read-write 0 Initialization from a FORCE_OUT is disabled. #0 1 Initialization from a FORCE_OUT is enabled. #1 INDEP Independent or Complementary Pair Operation 13 1 read-write 0 PWM_A and PWM_B form a complementary PWM pair. #0 1 PWM_A and PWM_B outputs are independent PWMs. #1 INIT_SEL Initialization Control Select 8 2 read-write 00 Local sync (PWM_X) causes initialization. #00 01 Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. #01 10 Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. #10 11 EXT_SYNC causes initialization. #11 PWM23_INIT PWM23 Initial Value 12 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWMX_INIT PWM_X Initial Value 10 1 read-write RELOAD_SEL Reload Source Select 2 1 read-write 0 The local RELOAD signal is used to reload registers. #0 1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. #1 WAITEN WAIT Enable 14 1 read-write SM1CVAL0 Capture Value 0 Register 0x120 16 read-only n 0x0 0x0 CAPTVAL0 This read-only register stores the value captured from the submodule counter 0 16 read-only SM1CVAL0CYC Capture Value 0 Cycle Register 0x126 16 read-only n 0x0 0x0 CVAL0CYC This read-only register stores the cycle number corresponding to the value captured in CVAL0 0 4 read-only SM1CVAL1 Capture Value 1 Register 0x12C 16 read-only n 0x0 0x0 CAPTVAL1 This read-only register stores the value captured from the submodule counter 0 16 read-only SM1CVAL1CYC Capture Value 1 Cycle Register 0x132 16 read-only n 0x0 0x0 CVAL1CYC This read-only register stores the cycle number corresponding to the value captured in CVAL1 0 4 read-only SM1CVAL2 Capture Value 2 Register 0x138 16 read-only n 0x0 0x0 CAPTVAL2 This read-only register stores the value captured from the submodule counter 0 16 read-only SM1CVAL2CYC Capture Value 2 Cycle Register 0x13E 16 read-only n 0x0 0x0 CVAL2CYC This read-only register stores the cycle number corresponding to the value captured in CVAL2 0 4 read-only SM1CVAL3 Capture Value 3 Register 0x144 16 read-only n 0x0 0x0 CAPTVAL3 This read-only register stores the value captured from the submodule counter 0 16 read-only SM1CVAL3CYC Capture Value 3 Cycle Register 0x14A 16 read-only n 0x0 0x0 CVAL3CYC This read-only register stores the cycle number corresponding to the value captured in CVAL3 0 4 read-only SM1CVAL4 Capture Value 4 Register 0x150 16 read-only n 0x0 0x0 CAPTVAL4 This read-only register stores the value captured from the submodule counter 0 16 read-only SM1CVAL4CYC Capture Value 4 Cycle Register 0x156 16 read-only n 0x0 0x0 CVAL4CYC This read-only register stores the cycle number corresponding to the value captured in CVAL4 0 4 read-only SM1CVAL5 Capture Value 5 Register 0x15C 16 read-only n 0x0 0x0 CAPTVAL5 This read-only register stores the value captured from the submodule counter 0 16 read-only SM1CVAL5CYC Capture Value 5 Cycle Register 0x162 16 read-only n 0x0 0x0 CVAL5CYC This read-only register stores the cycle number corresponding to the value captured in CVAL5 0 4 read-only SM1DISMAP0 Fault Disable Mapping Register 0 0xE4 16 read-write n 0x0 0x0 DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write SM1DMAEN DMA Enable Register 0xD8 16 read-write n 0x0 0x0 CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write 00 Read DMA requests disabled. #00 01 Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. #01 10 A local sync (VAL1 matches counter) sets the read DMA request. #10 11 A local reload (STS[RF] being set) sets the read DMA request. #11 CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write FAND FIFO Watermark AND Control 8 1 read-write 0 Selected FIFO watermarks are OR'ed together. #0 1 Selected FIFO watermarks are AND'ed together. #1 VALDE Value Registers DMA Enable 9 1 read-write 0 DMA write requests disabled #0 1 DMA write requests for the VALx and FRACVALx registers enabled #1 SM1DTCNT0 Deadtime Count Register 0 0xF0 16 read-write n 0x0 0x0 DTCNT0 The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC23_EN] is set) 0 16 read-write SM1DTCNT1 Deadtime Count Register 1 0xF6 16 read-write n 0x0 0x0 DTCNT1 The DTCNT1 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC45_EN] is set) 0 16 read-write SM1FRACVAL1 Fractional Value Register 1 0x84 16 read-write n 0x0 0x0 FRACVAL1 Fractional Value 1 Register 11 5 read-write SM1FRACVAL2 Fractional Value Register 2 0x90 16 read-write n 0x0 0x0 FRACVAL2 Fractional Value 2 11 5 read-write SM1FRACVAL3 Fractional Value Register 3 0x9C 16 read-write n 0x0 0x0 FRACVAL3 Fractional Value 3 11 5 read-write SM1FRACVAL4 Fractional Value Register 4 0xA8 16 read-write n 0x0 0x0 FRACVAL4 Fractional Value 4 11 5 read-write SM1FRACVAL5 Fractional Value Register 5 0xB4 16 read-write n 0x0 0x0 FRACVAL5 Fractional Value 5 11 5 read-write SM1FRCTRL Fractional Control Register 0xC0 16 read-write n 0x0 0x0 FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write 0 Disable fractional cycle length for the PWM period. #0 1 Enable fractional cycle length for the PWM period. #1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write 0 Disable fractional cycle placement for PWM_A. #0 1 Enable fractional cycle placement for PWM_A. #1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write 0 Disable fractional cycle placement for PWM_B. #0 1 Enable fractional cycle placement for PWM_B. #1 FRAC_PU Fractional Delay Circuit Power Up 8 1 read-write 0 Turn off fractional delay logic. #0 1 Power up fractional delay logic. #1 TEST Test Status Bit 15 1 read-only SM1INIT Initial Count Register 0x66 16 read-write n 0x0 0x0 INIT Initial Count Register Bits 0 16 read-write SM1INTEN Interrupt Enable Register 0xD2 16 read-write n 0x0 0x0 CA0IE Capture A 0 Interrupt Enable 10 1 read-write 0 Interrupt request disabled for STS[CFA0]. #0 1 Interrupt request enabled for STS[CFA0]. #1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write 0 Interrupt request disabled for STS[CFA1]. #0 1 Interrupt request enabled for STS[CFA1]. #1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write 0 Interrupt request disabled for STS[CFB0]. #0 1 Interrupt request enabled for STS[CFB0]. #1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write 0 Interrupt request disabled for STS[CFB1]. #0 1 Interrupt request enabled for STS[CFB1]. #1 CMPIE Compare Interrupt Enables 0 6 read-write 0 The corresponding STS[CMPF] bit will not cause an interrupt request. #0 1 The corresponding STS[CMPF] bit will cause an interrupt request. #1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write 0 Interrupt request disabled for STS[CFX0]. #0 1 Interrupt request enabled for STS[CFX0]. #1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write 0 Interrupt request disabled for STS[CFX1]. #0 1 Interrupt request enabled for STS[CFX1]. #1 REIE Reload Error Interrupt Enable 13 1 read-write 0 STS[REF] CPU interrupt requests disabled #0 1 STS[REF] CPU interrupt requests enabled #1 RIE Reload Interrupt Enable 12 1 read-write 0 STS[RF] CPU interrupt requests disabled #0 1 STS[RF] CPU interrupt requests enabled #1 SM1OCTRL Output Control Register 0xC6 16 read-write n 0x0 0x0 POLA PWM_A Output Polarity 10 1 read-write 0 PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. #0 1 PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. #1 POLB PWM_B Output Polarity 9 1 read-write 0 PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. #0 1 PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. #1 POLX PWM_X Output Polarity 8 1 read-write 0 PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. #0 1 PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. #1 PWMAFS PWM_A Fault State 4 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMA_IN PWM_A Input 15 1 read-only PWMBFS PWM_B Fault State 2 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMB_IN PWM_B Input 14 1 read-only PWMXFS PWM_X Fault State 0 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMX_IN PWM_X Input 13 1 read-only SM1STS Status Register 0xCC 16 read-write n 0x0 0x0 CFA0 Capture Flag A0 10 1 read-write CFA1 Capture Flag A1 11 1 read-write CFB0 Capture Flag B0 8 1 read-write CFB1 Capture Flag B1 9 1 read-write CFX0 Capture Flag X0 6 1 read-write CFX1 Capture Flag X1 7 1 read-write CMPF Compare Flags 0 6 read-write 0 No compare event has occurred for a particular VALx value. #0 1 A compare event has occurred for a particular VALx value. #1 REF Reload Error Flag 13 1 read-write 0 No reload error occurred. #0 1 Reload signal occurred with non-coherent data and MCTRL0[LDOK] = 0. #1 RF Reload Flag 12 1 read-write 0 No new reload cycle since last STS[RF] clearing #0 1 New reload cycle since last STS[RF] clearing #1 RUF Registers Updated Flag 14 1 read-only 0 No register update has occurred since last reload. #0 1 At least one of the double buffered registers has been updated since the last reload. #1 SM1TCTRL Output Trigger Control Register 0xDE 16 read-write n 0x0 0x0 OUT_TRIG_EN Output Trigger Enables 0 6 read-write 0 PWM_OUT_TRIGx will not set when the counter value matches the VALx value. #0 1 PWM_OUT_TRIGx will set when the counter value matches the VALx value. #1 PWAOT0 Output Trigger 0 Source Select 15 1 read-write 0 Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. #0 1 Route the PWM0 output to the PWM_OUT_TRIG0 port. #1 PWBOT1 Output Trigger 1 Source Select 14 1 read-write 0 Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. #0 1 Route the PWM1 output to the PWM_OUT_TRIG1 port. #1 TRGFRQ Trigger frequency 12 1 read-write 0 Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #0 1 Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #1 SM1VAL0 Value Register 0 0x7E 16 read-write n 0x0 0x0 VAL0 Value Register 0 0 16 read-write SM1VAL1 Value Register 1 0x8A 16 read-write n 0x0 0x0 VAL1 Value Register 1 0 16 read-write SM1VAL2 Value Register 2 0x96 16 read-write n 0x0 0x0 VAL2 Value Register 2 0 16 read-write SM1VAL3 Value Register 3 0xA2 16 read-write n 0x0 0x0 VAL3 Value Register 3 0 16 read-write SM1VAL4 Value Register 4 0xAE 16 read-write n 0x0 0x0 VAL4 Value Register 4 0 16 read-write SM1VAL5 Value Register 5 0xBA 16 read-write n 0x0 0x0 VAL5 Value Register 5 0 16 read-write SM2CAPTCOMPA Capture Compare A Register 0x1F8 16 read-write n 0x0 0x0 EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only SM2CAPTCOMPB Capture Compare B Register 0x208 16 read-write n 0x0 0x0 EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only SM2CAPTCOMPX Capture Compare X Register 0x218 16 read-write n 0x0 0x0 EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only SM2CAPTCTRLA Capture Control A Register 0x1F0 16 read-write n 0x0 0x0 ARMA Arm A 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. #1 CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only CFAWM Capture A FIFOs Water Mark 8 2 read-write EDGA0 Edge A 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGA1 Edge A 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTA_EN Edge Counter A Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELA Input Select A 6 1 read-write 0 Raw PWM_A input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. #1 ONESHOTA One Shot Mode A 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. #1 SM2CAPTCTRLB Capture Control B Register 0x200 16 read-write n 0x0 0x0 ARMB Arm B 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. #1 CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only CFBWM Capture B FIFOs Water Mark 8 2 read-write EDGB0 Edge B 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGB1 Edge B 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTB_EN Edge Counter B Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELB Input Select B 6 1 read-write 0 Raw PWM_B input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. #1 ONESHOTB One Shot Mode B 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. #1 SM2CAPTCTRLX Capture Control X Register 0x210 16 read-write n 0x0 0x0 ARMX Arm X 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. #1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only EDGCNTX_EN Edge Counter X Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 EDGX0 Edge X 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGX1 Edge X 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 INP_SELX Input Select X 6 1 read-write 0 Raw PWM_X input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. #1 ONESHOTX One Shot Mode Aux 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. #1 SM2CNT Counter Register 0x120 16 read-only n 0x0 0x0 CNT Counter Register Bits 0 16 read-only SM2CTRL Control Register 0x138 16 read-write n 0x0 0x0 DBLEN Double Switching Enable 0 1 read-write 0 Double switching disabled. #0 1 Double switching enabled. #1 DBLX PWMX Double Switching Enable 1 1 read-write 0 PWMX double pulse disabled. #0 1 PWMX double pulse enabled. #1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write 0 Full-cycle reloads disabled. #0 1 Full-cycle reloads enabled. #1 HALF Half Cycle Reload 11 1 read-write 0 Half-cycle reloads disabled. #0 1 Half-cycle reloads enabled. #1 LDFQ Load Frequency 12 4 read-write 0000 Every PWM opportunity #0000 0001 Every 2 PWM opportunities #0001 0010 Every 3 PWM opportunities #0010 0011 Every 4 PWM opportunities #0011 0100 Every 5 PWM opportunities #0100 0101 Every 6 PWM opportunities #0101 0110 Every 7 PWM opportunities #0110 0111 Every 8 PWM opportunities #0111 1000 Every 9 PWM opportunities #1000 1001 Every 10 PWM opportunities #1001 1010 Every 11 PWM opportunities #1010 1011 Every 12 PWM opportunities #1011 1100 Every 13 PWM opportunities #1100 1101 Every 14 PWM opportunities #1101 1110 Every 15 PWM opportunities #1110 1111 Every 16 PWM opportunities #1111 LDMOD Load Mode Select 2 1 read-write 0 Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set. #0 1 Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. #1 PRSC Prescaler 4 3 read-write 000 PWM clock frequency = fclk #000 001 PWM clock frequency = fclk/2 #001 010 PWM clock frequency = fclk/4 #010 011 PWM clock frequency = fclk/8 #011 100 PWM clock frequency = fclk/16 #100 101 PWM clock frequency = fclk/32 #101 110 PWM clock frequency = fclk/64 #110 111 PWM clock frequency = fclk/128 #111 SM2CTRL2 Control 2 Register 0x130 16 read-write n 0x0 0x0 CLK_SEL Clock Source Select 0 2 read-write 00 The IPBus clock is used as the clock for the local prescaler and counter. #00 01 EXT_CLK is used as the clock for the local prescaler and counter. #01 10 Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. #10 DBGEN Debug Enable 15 1 read-write FORCE Force Initialization 6 1 write-only FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write 000 The local force signal, CTRL2[FORCE], from this submodule is used to force updates. #000 001 The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. #001 010 The local reload signal from this submodule is used to force updates without regard to the state of LDOK. #010 011 The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #011 100 The local sync signal from this submodule is used to force updates. #100 101 The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #101 110 The external force signal, EXT_FORCE, from outside the PWM module causes updates. #110 111 The external sync signal, EXT_SYNC, from outside the PWM module causes updates. #111 FRCEN This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by CTRL2[INIT_SEL] 7 1 read-write 0 Initialization from a FORCE_OUT is disabled. #0 1 Initialization from a FORCE_OUT is enabled. #1 INDEP Independent or Complementary Pair Operation 13 1 read-write 0 PWM_A and PWM_B form a complementary PWM pair. #0 1 PWM_A and PWM_B outputs are independent PWMs. #1 INIT_SEL Initialization Control Select 8 2 read-write 00 Local sync (PWM_X) causes initialization. #00 01 Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. #01 10 Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. #10 11 EXT_SYNC causes initialization. #11 PWM23_INIT PWM23 Initial Value 12 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWMX_INIT PWM_X Initial Value 10 1 read-write RELOAD_SEL Reload Source Select 2 1 read-write 0 The local RELOAD signal is used to reload registers. #0 1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. #1 WAITEN WAIT Enable 14 1 read-write SM2CVAL0 Capture Value 0 Register 0x220 16 read-only n 0x0 0x0 CAPTVAL0 This read-only register stores the value captured from the submodule counter 0 16 read-only SM2CVAL0CYC Capture Value 0 Cycle Register 0x228 16 read-only n 0x0 0x0 CVAL0CYC This read-only register stores the cycle number corresponding to the value captured in CVAL0 0 4 read-only SM2CVAL1 Capture Value 1 Register 0x230 16 read-only n 0x0 0x0 CAPTVAL1 This read-only register stores the value captured from the submodule counter 0 16 read-only SM2CVAL1CYC Capture Value 1 Cycle Register 0x238 16 read-only n 0x0 0x0 CVAL1CYC This read-only register stores the cycle number corresponding to the value captured in CVAL1 0 4 read-only SM2CVAL2 Capture Value 2 Register 0x240 16 read-only n 0x0 0x0 CAPTVAL2 This read-only register stores the value captured from the submodule counter 0 16 read-only SM2CVAL2CYC Capture Value 2 Cycle Register 0x248 16 read-only n 0x0 0x0 CVAL2CYC This read-only register stores the cycle number corresponding to the value captured in CVAL2 0 4 read-only SM2CVAL3 Capture Value 3 Register 0x250 16 read-only n 0x0 0x0 CAPTVAL3 This read-only register stores the value captured from the submodule counter 0 16 read-only SM2CVAL3CYC Capture Value 3 Cycle Register 0x258 16 read-only n 0x0 0x0 CVAL3CYC This read-only register stores the cycle number corresponding to the value captured in CVAL3 0 4 read-only SM2CVAL4 Capture Value 4 Register 0x260 16 read-only n 0x0 0x0 CAPTVAL4 This read-only register stores the value captured from the submodule counter 0 16 read-only SM2CVAL4CYC Capture Value 4 Cycle Register 0x268 16 read-only n 0x0 0x0 CVAL4CYC This read-only register stores the cycle number corresponding to the value captured in CVAL4 0 4 read-only SM2CVAL5 Capture Value 5 Register 0x270 16 read-only n 0x0 0x0 CAPTVAL5 This read-only register stores the value captured from the submodule counter 0 16 read-only SM2CVAL5CYC Capture Value 5 Cycle Register 0x278 16 read-only n 0x0 0x0 CVAL5CYC This read-only register stores the cycle number corresponding to the value captured in CVAL5 0 4 read-only SM2DISMAP0 Fault Disable Mapping Register 0 0x1D0 16 read-write n 0x0 0x0 DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write SM2DMAEN DMA Enable Register 0x1C0 16 read-write n 0x0 0x0 CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write 00 Read DMA requests disabled. #00 01 Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. #01 10 A local sync (VAL1 matches counter) sets the read DMA request. #10 11 A local reload (STS[RF] being set) sets the read DMA request. #11 CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write FAND FIFO Watermark AND Control 8 1 read-write 0 Selected FIFO watermarks are OR'ed together. #0 1 Selected FIFO watermarks are AND'ed together. #1 VALDE Value Registers DMA Enable 9 1 read-write 0 DMA write requests disabled #0 1 DMA write requests for the VALx and FRACVALx registers enabled #1 SM2DTCNT0 Deadtime Count Register 0 0x1E0 16 read-write n 0x0 0x0 DTCNT0 The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC23_EN] is set) 0 16 read-write SM2DTCNT1 Deadtime Count Register 1 0x1E8 16 read-write n 0x0 0x0 DTCNT1 The DTCNT1 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC45_EN] is set) 0 16 read-write SM2FRACVAL1 Fractional Value Register 1 0x150 16 read-write n 0x0 0x0 FRACVAL1 Fractional Value 1 Register 11 5 read-write SM2FRACVAL2 Fractional Value Register 2 0x160 16 read-write n 0x0 0x0 FRACVAL2 Fractional Value 2 11 5 read-write SM2FRACVAL3 Fractional Value Register 3 0x170 16 read-write n 0x0 0x0 FRACVAL3 Fractional Value 3 11 5 read-write SM2FRACVAL4 Fractional Value Register 4 0x180 16 read-write n 0x0 0x0 FRACVAL4 Fractional Value 4 11 5 read-write SM2FRACVAL5 Fractional Value Register 5 0x190 16 read-write n 0x0 0x0 FRACVAL5 Fractional Value 5 11 5 read-write SM2FRCTRL Fractional Control Register 0x1A0 16 read-write n 0x0 0x0 FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write 0 Disable fractional cycle length for the PWM period. #0 1 Enable fractional cycle length for the PWM period. #1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write 0 Disable fractional cycle placement for PWM_A. #0 1 Enable fractional cycle placement for PWM_A. #1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write 0 Disable fractional cycle placement for PWM_B. #0 1 Enable fractional cycle placement for PWM_B. #1 FRAC_PU Fractional Delay Circuit Power Up 8 1 read-write 0 Turn off fractional delay logic. #0 1 Power up fractional delay logic. #1 TEST Test Status Bit 15 1 read-only SM2INIT Initial Count Register 0x128 16 read-write n 0x0 0x0 INIT Initial Count Register Bits 0 16 read-write SM2INTEN Interrupt Enable Register 0x1B8 16 read-write n 0x0 0x0 CA0IE Capture A 0 Interrupt Enable 10 1 read-write 0 Interrupt request disabled for STS[CFA0]. #0 1 Interrupt request enabled for STS[CFA0]. #1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write 0 Interrupt request disabled for STS[CFA1]. #0 1 Interrupt request enabled for STS[CFA1]. #1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write 0 Interrupt request disabled for STS[CFB0]. #0 1 Interrupt request enabled for STS[CFB0]. #1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write 0 Interrupt request disabled for STS[CFB1]. #0 1 Interrupt request enabled for STS[CFB1]. #1 CMPIE Compare Interrupt Enables 0 6 read-write 0 The corresponding STS[CMPF] bit will not cause an interrupt request. #0 1 The corresponding STS[CMPF] bit will cause an interrupt request. #1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write 0 Interrupt request disabled for STS[CFX0]. #0 1 Interrupt request enabled for STS[CFX0]. #1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write 0 Interrupt request disabled for STS[CFX1]. #0 1 Interrupt request enabled for STS[CFX1]. #1 REIE Reload Error Interrupt Enable 13 1 read-write 0 STS[REF] CPU interrupt requests disabled #0 1 STS[REF] CPU interrupt requests enabled #1 RIE Reload Interrupt Enable 12 1 read-write 0 STS[RF] CPU interrupt requests disabled #0 1 STS[RF] CPU interrupt requests enabled #1 SM2OCTRL Output Control Register 0x1A8 16 read-write n 0x0 0x0 POLA PWM_A Output Polarity 10 1 read-write 0 PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. #0 1 PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. #1 POLB PWM_B Output Polarity 9 1 read-write 0 PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. #0 1 PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. #1 POLX PWM_X Output Polarity 8 1 read-write 0 PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. #0 1 PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. #1 PWMAFS PWM_A Fault State 4 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMA_IN PWM_A Input 15 1 read-only PWMBFS PWM_B Fault State 2 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMB_IN PWM_B Input 14 1 read-only PWMXFS PWM_X Fault State 0 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMX_IN PWM_X Input 13 1 read-only SM2STS Status Register 0x1B0 16 read-write n 0x0 0x0 CFA0 Capture Flag A0 10 1 read-write CFA1 Capture Flag A1 11 1 read-write CFB0 Capture Flag B0 8 1 read-write CFB1 Capture Flag B1 9 1 read-write CFX0 Capture Flag X0 6 1 read-write CFX1 Capture Flag X1 7 1 read-write CMPF Compare Flags 0 6 read-write 0 No compare event has occurred for a particular VALx value. #0 1 A compare event has occurred for a particular VALx value. #1 REF Reload Error Flag 13 1 read-write 0 No reload error occurred. #0 1 Reload signal occurred with non-coherent data and MCTRL0[LDOK] = 0. #1 RF Reload Flag 12 1 read-write 0 No new reload cycle since last STS[RF] clearing #0 1 New reload cycle since last STS[RF] clearing #1 RUF Registers Updated Flag 14 1 read-only 0 No register update has occurred since last reload. #0 1 At least one of the double buffered registers has been updated since the last reload. #1 SM2TCTRL Output Trigger Control Register 0x1C8 16 read-write n 0x0 0x0 OUT_TRIG_EN Output Trigger Enables 0 6 read-write 0 PWM_OUT_TRIGx will not set when the counter value matches the VALx value. #0 1 PWM_OUT_TRIGx will set when the counter value matches the VALx value. #1 PWAOT0 Output Trigger 0 Source Select 15 1 read-write 0 Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. #0 1 Route the PWM0 output to the PWM_OUT_TRIG0 port. #1 PWBOT1 Output Trigger 1 Source Select 14 1 read-write 0 Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. #0 1 Route the PWM1 output to the PWM_OUT_TRIG1 port. #1 TRGFRQ Trigger frequency 12 1 read-write 0 Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #0 1 Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #1 SM2VAL0 Value Register 0 0x148 16 read-write n 0x0 0x0 VAL0 Value Register 0 0 16 read-write SM2VAL1 Value Register 1 0x158 16 read-write n 0x0 0x0 VAL1 Value Register 1 0 16 read-write SM2VAL2 Value Register 2 0x168 16 read-write n 0x0 0x0 VAL2 Value Register 2 0 16 read-write SM2VAL3 Value Register 3 0x178 16 read-write n 0x0 0x0 VAL3 Value Register 3 0 16 read-write SM2VAL4 Value Register 4 0x188 16 read-write n 0x0 0x0 VAL4 Value Register 4 0 16 read-write SM2VAL5 Value Register 5 0x198 16 read-write n 0x0 0x0 VAL5 Value Register 5 0 16 read-write SM3CAPTCOMPA Capture Compare A Register 0x34E 16 read-write n 0x0 0x0 EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only SM3CAPTCOMPB Capture Compare B Register 0x362 16 read-write n 0x0 0x0 EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only SM3CAPTCOMPX Capture Compare X Register 0x376 16 read-write n 0x0 0x0 EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only SM3CAPTCTRLA Capture Control A Register 0x344 16 read-write n 0x0 0x0 ARMA Arm A 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. #1 CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only CFAWM Capture A FIFOs Water Mark 8 2 read-write EDGA0 Edge A 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGA1 Edge A 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTA_EN Edge Counter A Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELA Input Select A 6 1 read-write 0 Raw PWM_A input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. #1 ONESHOTA One Shot Mode A 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. #1 SM3CAPTCTRLB Capture Control B Register 0x358 16 read-write n 0x0 0x0 ARMB Arm B 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. #1 CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only CFBWM Capture B FIFOs Water Mark 8 2 read-write EDGB0 Edge B 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGB1 Edge B 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTB_EN Edge Counter B Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELB Input Select B 6 1 read-write 0 Raw PWM_B input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. #1 ONESHOTB One Shot Mode B 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. #1 SM3CAPTCTRLX Capture Control X Register 0x36C 16 read-write n 0x0 0x0 ARMX Arm X 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. #1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only EDGCNTX_EN Edge Counter X Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 EDGX0 Edge X 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGX1 Edge X 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 INP_SELX Input Select X 6 1 read-write 0 Raw PWM_X input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. #1 ONESHOTX One Shot Mode Aux 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. #1 SM3CNT Counter Register 0x240 16 read-only n 0x0 0x0 CNT Counter Register Bits 0 16 read-only SM3CTRL Control Register 0x25E 16 read-write n 0x0 0x0 DBLEN Double Switching Enable 0 1 read-write 0 Double switching disabled. #0 1 Double switching enabled. #1 DBLX PWMX Double Switching Enable 1 1 read-write 0 PWMX double pulse disabled. #0 1 PWMX double pulse enabled. #1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write 0 Full-cycle reloads disabled. #0 1 Full-cycle reloads enabled. #1 HALF Half Cycle Reload 11 1 read-write 0 Half-cycle reloads disabled. #0 1 Half-cycle reloads enabled. #1 LDFQ Load Frequency 12 4 read-write 0000 Every PWM opportunity #0000 0001 Every 2 PWM opportunities #0001 0010 Every 3 PWM opportunities #0010 0011 Every 4 PWM opportunities #0011 0100 Every 5 PWM opportunities #0100 0101 Every 6 PWM opportunities #0101 0110 Every 7 PWM opportunities #0110 0111 Every 8 PWM opportunities #0111 1000 Every 9 PWM opportunities #1000 1001 Every 10 PWM opportunities #1001 1010 Every 11 PWM opportunities #1010 1011 Every 12 PWM opportunities #1011 1100 Every 13 PWM opportunities #1100 1101 Every 14 PWM opportunities #1101 1110 Every 15 PWM opportunities #1110 1111 Every 16 PWM opportunities #1111 LDMOD Load Mode Select 2 1 read-write 0 Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set. #0 1 Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. #1 PRSC Prescaler 4 3 read-write 000 PWM clock frequency = fclk #000 001 PWM clock frequency = fclk/2 #001 010 PWM clock frequency = fclk/4 #010 011 PWM clock frequency = fclk/8 #011 100 PWM clock frequency = fclk/16 #100 101 PWM clock frequency = fclk/32 #101 110 PWM clock frequency = fclk/64 #110 111 PWM clock frequency = fclk/128 #111 SM3CTRL2 Control 2 Register 0x254 16 read-write n 0x0 0x0 CLK_SEL Clock Source Select 0 2 read-write 00 The IPBus clock is used as the clock for the local prescaler and counter. #00 01 EXT_CLK is used as the clock for the local prescaler and counter. #01 10 Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. #10 DBGEN Debug Enable 15 1 read-write FORCE Force Initialization 6 1 write-only FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write 000 The local force signal, CTRL2[FORCE], from this submodule is used to force updates. #000 001 The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. #001 010 The local reload signal from this submodule is used to force updates without regard to the state of LDOK. #010 011 The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #011 100 The local sync signal from this submodule is used to force updates. #100 101 The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #101 110 The external force signal, EXT_FORCE, from outside the PWM module causes updates. #110 111 The external sync signal, EXT_SYNC, from outside the PWM module causes updates. #111 FRCEN This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by CTRL2[INIT_SEL] 7 1 read-write 0 Initialization from a FORCE_OUT is disabled. #0 1 Initialization from a FORCE_OUT is enabled. #1 INDEP Independent or Complementary Pair Operation 13 1 read-write 0 PWM_A and PWM_B form a complementary PWM pair. #0 1 PWM_A and PWM_B outputs are independent PWMs. #1 INIT_SEL Initialization Control Select 8 2 read-write 00 Local sync (PWM_X) causes initialization. #00 01 Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. #01 10 Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. #10 11 EXT_SYNC causes initialization. #11 PWM23_INIT PWM23 Initial Value 12 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWMX_INIT PWM_X Initial Value 10 1 read-write RELOAD_SEL Reload Source Select 2 1 read-write 0 The local RELOAD signal is used to reload registers. #0 1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. #1 WAITEN WAIT Enable 14 1 read-write SM3CVAL0 Capture Value 0 Register 0x380 16 read-only n 0x0 0x0 CAPTVAL0 This read-only register stores the value captured from the submodule counter 0 16 read-only SM3CVAL0CYC Capture Value 0 Cycle Register 0x38A 16 read-only n 0x0 0x0 CVAL0CYC This read-only register stores the cycle number corresponding to the value captured in CVAL0 0 4 read-only SM3CVAL1 Capture Value 1 Register 0x394 16 read-only n 0x0 0x0 CAPTVAL1 This read-only register stores the value captured from the submodule counter 0 16 read-only SM3CVAL1CYC Capture Value 1 Cycle Register 0x39E 16 read-only n 0x0 0x0 CVAL1CYC This read-only register stores the cycle number corresponding to the value captured in CVAL1 0 4 read-only SM3CVAL2 Capture Value 2 Register 0x3A8 16 read-only n 0x0 0x0 CAPTVAL2 This read-only register stores the value captured from the submodule counter 0 16 read-only SM3CVAL2CYC Capture Value 2 Cycle Register 0x3B2 16 read-only n 0x0 0x0 CVAL2CYC This read-only register stores the cycle number corresponding to the value captured in CVAL2 0 4 read-only SM3CVAL3 Capture Value 3 Register 0x3BC 16 read-only n 0x0 0x0 CAPTVAL3 This read-only register stores the value captured from the submodule counter 0 16 read-only SM3CVAL3CYC Capture Value 3 Cycle Register 0x3C6 16 read-only n 0x0 0x0 CVAL3CYC This read-only register stores the cycle number corresponding to the value captured in CVAL3 0 4 read-only SM3CVAL4 Capture Value 4 Register 0x3D0 16 read-only n 0x0 0x0 CAPTVAL4 This read-only register stores the value captured from the submodule counter 0 16 read-only SM3CVAL4CYC Capture Value 4 Cycle Register 0x3DA 16 read-only n 0x0 0x0 CVAL4CYC This read-only register stores the cycle number corresponding to the value captured in CVAL4 0 4 read-only SM3CVAL5 Capture Value 5 Register 0x3E4 16 read-only n 0x0 0x0 CAPTVAL5 This read-only register stores the value captured from the submodule counter 0 16 read-only SM3CVAL5CYC Capture Value 5 Cycle Register 0x3EE 16 read-only n 0x0 0x0 CVAL5CYC This read-only register stores the cycle number corresponding to the value captured in CVAL5 0 4 read-only SM3DISMAP0 Fault Disable Mapping Register 0 0x31C 16 read-write n 0x0 0x0 DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write SM3DMAEN DMA Enable Register 0x308 16 read-write n 0x0 0x0 CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write 00 Read DMA requests disabled. #00 01 Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. #01 10 A local sync (VAL1 matches counter) sets the read DMA request. #10 11 A local reload (STS[RF] being set) sets the read DMA request. #11 CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write FAND FIFO Watermark AND Control 8 1 read-write 0 Selected FIFO watermarks are OR'ed together. #0 1 Selected FIFO watermarks are AND'ed together. #1 VALDE Value Registers DMA Enable 9 1 read-write 0 DMA write requests disabled #0 1 DMA write requests for the VALx and FRACVALx registers enabled #1 SM3DTCNT0 Deadtime Count Register 0 0x330 16 read-write n 0x0 0x0 DTCNT0 The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC23_EN] is set) 0 16 read-write SM3DTCNT1 Deadtime Count Register 1 0x33A 16 read-write n 0x0 0x0 DTCNT1 The DTCNT1 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC45_EN] is set) 0 16 read-write SM3FRACVAL1 Fractional Value Register 1 0x27C 16 read-write n 0x0 0x0 FRACVAL1 Fractional Value 1 Register 11 5 read-write SM3FRACVAL2 Fractional Value Register 2 0x290 16 read-write n 0x0 0x0 FRACVAL2 Fractional Value 2 11 5 read-write SM3FRACVAL3 Fractional Value Register 3 0x2A4 16 read-write n 0x0 0x0 FRACVAL3 Fractional Value 3 11 5 read-write SM3FRACVAL4 Fractional Value Register 4 0x2B8 16 read-write n 0x0 0x0 FRACVAL4 Fractional Value 4 11 5 read-write SM3FRACVAL5 Fractional Value Register 5 0x2CC 16 read-write n 0x0 0x0 FRACVAL5 Fractional Value 5 11 5 read-write SM3FRCTRL Fractional Control Register 0x2E0 16 read-write n 0x0 0x0 FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write 0 Disable fractional cycle length for the PWM period. #0 1 Enable fractional cycle length for the PWM period. #1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write 0 Disable fractional cycle placement for PWM_A. #0 1 Enable fractional cycle placement for PWM_A. #1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write 0 Disable fractional cycle placement for PWM_B. #0 1 Enable fractional cycle placement for PWM_B. #1 FRAC_PU Fractional Delay Circuit Power Up 8 1 read-write 0 Turn off fractional delay logic. #0 1 Power up fractional delay logic. #1 TEST Test Status Bit 15 1 read-only SM3INIT Initial Count Register 0x24A 16 read-write n 0x0 0x0 INIT Initial Count Register Bits 0 16 read-write SM3INTEN Interrupt Enable Register 0x2FE 16 read-write n 0x0 0x0 CA0IE Capture A 0 Interrupt Enable 10 1 read-write 0 Interrupt request disabled for STS[CFA0]. #0 1 Interrupt request enabled for STS[CFA0]. #1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write 0 Interrupt request disabled for STS[CFA1]. #0 1 Interrupt request enabled for STS[CFA1]. #1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write 0 Interrupt request disabled for STS[CFB0]. #0 1 Interrupt request enabled for STS[CFB0]. #1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write 0 Interrupt request disabled for STS[CFB1]. #0 1 Interrupt request enabled for STS[CFB1]. #1 CMPIE Compare Interrupt Enables 0 6 read-write 0 The corresponding STS[CMPF] bit will not cause an interrupt request. #0 1 The corresponding STS[CMPF] bit will cause an interrupt request. #1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write 0 Interrupt request disabled for STS[CFX0]. #0 1 Interrupt request enabled for STS[CFX0]. #1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write 0 Interrupt request disabled for STS[CFX1]. #0 1 Interrupt request enabled for STS[CFX1]. #1 REIE Reload Error Interrupt Enable 13 1 read-write 0 STS[REF] CPU interrupt requests disabled #0 1 STS[REF] CPU interrupt requests enabled #1 RIE Reload Interrupt Enable 12 1 read-write 0 STS[RF] CPU interrupt requests disabled #0 1 STS[RF] CPU interrupt requests enabled #1 SM3OCTRL Output Control Register 0x2EA 16 read-write n 0x0 0x0 POLA PWM_A Output Polarity 10 1 read-write 0 PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. #0 1 PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. #1 POLB PWM_B Output Polarity 9 1 read-write 0 PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. #0 1 PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. #1 POLX PWM_X Output Polarity 8 1 read-write 0 PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. #0 1 PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. #1 PWMAFS PWM_A Fault State 4 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMA_IN PWM_A Input 15 1 read-only PWMBFS PWM_B Fault State 2 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMB_IN PWM_B Input 14 1 read-only PWMXFS PWM_X Fault State 0 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMX_IN PWM_X Input 13 1 read-only SM3STS Status Register 0x2F4 16 read-write n 0x0 0x0 CFA0 Capture Flag A0 10 1 read-write CFA1 Capture Flag A1 11 1 read-write CFB0 Capture Flag B0 8 1 read-write CFB1 Capture Flag B1 9 1 read-write CFX0 Capture Flag X0 6 1 read-write CFX1 Capture Flag X1 7 1 read-write CMPF Compare Flags 0 6 read-write 0 No compare event has occurred for a particular VALx value. #0 1 A compare event has occurred for a particular VALx value. #1 REF Reload Error Flag 13 1 read-write 0 No reload error occurred. #0 1 Reload signal occurred with non-coherent data and MCTRL0[LDOK] = 0. #1 RF Reload Flag 12 1 read-write 0 No new reload cycle since last STS[RF] clearing #0 1 New reload cycle since last STS[RF] clearing #1 RUF Registers Updated Flag 14 1 read-only 0 No register update has occurred since last reload. #0 1 At least one of the double buffered registers has been updated since the last reload. #1 SM3TCTRL Output Trigger Control Register 0x312 16 read-write n 0x0 0x0 OUT_TRIG_EN Output Trigger Enables 0 6 read-write 0 PWM_OUT_TRIGx will not set when the counter value matches the VALx value. #0 1 PWM_OUT_TRIGx will set when the counter value matches the VALx value. #1 PWAOT0 Output Trigger 0 Source Select 15 1 read-write 0 Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. #0 1 Route the PWM0 output to the PWM_OUT_TRIG0 port. #1 PWBOT1 Output Trigger 1 Source Select 14 1 read-write 0 Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. #0 1 Route the PWM1 output to the PWM_OUT_TRIG1 port. #1 TRGFRQ Trigger frequency 12 1 read-write 0 Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #0 1 Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #1 SM3VAL0 Value Register 0 0x272 16 read-write n 0x0 0x0 VAL0 Value Register 0 0 16 read-write SM3VAL1 Value Register 1 0x286 16 read-write n 0x0 0x0 VAL1 Value Register 1 0 16 read-write SM3VAL2 Value Register 2 0x29A 16 read-write n 0x0 0x0 VAL2 Value Register 2 0 16 read-write SM3VAL3 Value Register 3 0x2AE 16 read-write n 0x0 0x0 VAL3 Value Register 3 0 16 read-write SM3VAL4 Value Register 4 0x2C2 16 read-write n 0x0 0x0 VAL4 Value Register 4 0 16 read-write SM3VAL5 Value Register 5 0x2D6 16 read-write n 0x0 0x0 VAL5 Value Register 5 0 16 read-write SWCOUT Software Controlled Output Register 0x184 16 read-write n 0x0 0x0 SM0OUT23 Submodule 0 Software Controlled Output 23 1 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. #0 1 A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. #1 SM0OUT45 Submodule 0 Software Controlled Output 45 0 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. #0 1 A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. #1 SM1OUT23 Submodule 1 Software Controlled Output 23 3 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. #0 1 A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. #1 SM1OUT45 Submodule 1 Software Controlled Output 45 2 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. #0 1 A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. #1 SM2OUT23 Submodule 2 Software Controlled Output 23 5 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. #0 1 A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. #1 SM2OUT45 Submodule 2 Software Controlled Output 45 4 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. #0 1 A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. #1 SM3OUT23 Submodule 3 Software Controlled Output 23 7 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. #0 1 A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. #1 SM3OUT45 Submodule 3 Software Controlled Output 45 6 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. #0 1 A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. #1 PWM1 Pulse Width Modulator with nano edge placement PWM 0x0 0x0 0x196 registers n PWM1_CMP0 104 PWM1_RELOAD0 105 PWM1_CMP1 106 PWM1_RELOAD1 107 PWM1_CMP2 108 PWM1_RELOAD2 109 PWM1_CMP3 110 PWM1_RELOAD3 111 PWM1_CAP 112 PWM1_RERR 113 PWM1_FAULT 114 DTSRCSEL PWM Source Select Register 0x186 16 read-write n 0x0 0x0 SM0SEL23 Submodule 0 PWM23 Control Select 2 2 read-write 00 Generated SM0PWM23 signal is used by the deadtime logic. #00 01 Inverted generated SM0PWM23 signal is used by the deadtime logic. #01 10 SWCOUT[SM0OUT23] is used by the deadtime logic. #10 11 PWMx_EXTA0 signal is used by the deadtime logic. #11 SM0SEL45 Submodule 0 PWM45 Control Select 0 2 read-write 00 Generated SM0PWM45 signal is used by the deadtime logic. #00 01 Inverted generated SM0PWM45 signal is used by the deadtime logic. #01 10 SWCOUT[SM0OUT45] is used by the deadtime logic. #10 11 PWMx_EXTB0 signal is used by the deadtime logic. #11 SM1SEL23 Submodule 1 PWM23 Control Select 6 2 read-write 00 Generated SM1PWM23 signal is used by the deadtime logic. #00 01 Inverted generated SM1PWM23 signal is used by the deadtime logic. #01 10 SWCOUT[SM1OUT23] is used by the deadtime logic. #10 11 PWMx_EXTA1 signal is used by the deadtime logic. #11 SM1SEL45 Submodule 1 PWM45 Control Select 4 2 read-write 00 Generated SM1PWM45 signal is used by the deadtime logic. #00 01 Inverted generated SM1PWM45 signal is used by the deadtime logic. #01 10 SWCOUT[SM1OUT45] is used by the deadtime logic. #10 11 PWMx_EXTB1 signal is used by the deadtime logic. #11 SM2SEL23 Submodule 2 PWM23 Control Select 10 2 read-write 00 Generated SM2PWM23 signal is used by the deadtime logic. #00 01 Inverted generated SM2PWM23 signal is used by the deadtime logic. #01 10 SWCOUT[SM2OUT23] is used by the deadtime logic. #10 11 PWMx_EXTA2 signal is used by the deadtime logic. #11 SM2SEL45 Submodule 2 PWM45 Control Select 8 2 read-write 00 Generated SM2PWM45 signal is used by the deadtime logic. #00 01 Inverted generated SM2PWM45 signal is used by the deadtime logic. #01 10 SWCOUT[SM2OUT45] is used by the deadtime logic. #10 11 PWMx_EXTB2 signal is used by the deadtime logic. #11 SM3SEL23 Submodule 3 PWM23 Control Select 14 2 read-write 00 Generated SM3PWM23 signal is used by the deadtime logic. #00 01 Inverted generated SM3PWM23 signal is used by the deadtime logic. #01 10 SWCOUT[SM3OUT23] is used by the deadtime logic. #10 11 PWMx_EXTA3 signal is used by the deadtime logic. #11 SM3SEL45 Submodule 3 PWM45 Control Select 12 2 read-write 00 Generated SM3PWM45 signal is used by the deadtime logic. #00 01 Inverted generated SM3PWM45 signal is used by the deadtime logic. #01 10 SWCOUT[SM3OUT45] is used by the deadtime logic. #10 11 PWMx_EXTB3 signal is used by the deadtime logic. #11 FCTRL Fault Control Register 0x18C 16 read-write n 0x0 0x0 FAUTO Automatic Fault Clearing 8 4 read-write 0 Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further controlled by FCTRL[FSAFE]. #0000 1 Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. #0001 FIE Fault Interrupt Enables 0 4 read-write 0 FAULTx CPU interrupt requests disabled. #0000 1 FAULTx CPU interrupt requests enabled. #0001 FLVL Fault Level 12 4 read-write 0 A logic 0 on the fault input indicates a fault condition. #0000 1 A logic 1 on the fault input indicates a fault condition. #0001 FSAFE Fault Safety Mode 4 4 read-write 0 Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). #0000 1 Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL]. #0001 FCTRL2 Fault Control 2 Register 0x194 16 read-write n 0x0 0x0 NOCOMB No Combinational Path From Fault Input To PWM Output 0 4 read-write 0 There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. #0000 1 The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs. #0001 FFILT Fault Filter Register 0x190 16 read-write n 0x0 0x0 FILT_CNT Fault Filter Count 8 3 read-write FILT_PER Fault Filter Period 0 8 read-write GSTR Fault Glitch Stretch Enable 15 1 read-write 0 Fault input glitch stretching is disabled. #0 1 Input fault signals will be stretched to at least 2 IPBus clock cycles. #1 FSTS Fault Status Register 0x18E 16 read-write n 0x0 0x0 FFLAG Fault Flags 0 4 read-write 0 No fault on the FAULTx pin. #0000 1 Fault on the FAULTx pin. #0001 FFPIN Filtered Fault Pins 8 4 read-only FFULL Full Cycle 4 4 read-write 0 PWM outputs are not re-enabled at the start of a full cycle #0000 1 PWM outputs are re-enabled at the start of a full cycle #0001 FHALF Half Cycle Fault Recovery 12 4 read-write 0 PWM outputs are not re-enabled at the start of a half cycle. #0000 1 PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). #0001 FTST Fault Test Register 0x192 16 read-write n 0x0 0x0 FTEST Fault Test 0 1 read-write 0 No fault #0 1 Cause a simulated fault #1 MASK Mask Register 0x182 16 read-write n 0x0 0x0 MASKA PWM_A Masks 8 4 read-write 0 PWM_A output normal. #0000 1 PWM_A output masked. #0001 MASKB PWM_B Masks 4 4 read-write 0 PWM_B output normal. #0000 1 PWM_B output masked. #0001 MASKX PWM_X Masks 0 4 read-write 0 PWM_X output normal. #0000 1 PWM_X output masked. #0001 UPDATE_MASK Update Mask Bits Immediately 12 4 write-only 0 Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. #0000 1 Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. #0001 MCTRL0 Master Control Register 0 0x188 16 read-write n 0x0 0x0 CLDOK Clear Load Okay 4 4 write-only IPOL Current Polarity 12 4 read-write 0 PWM23 is used to generate complementary PWM pair in the corresponding submodule. #0000 1 PWM45 is used to generate complementary PWM pair in the corresponding submodule. #0001 LDOK Load Okay 0 4 read-write 0 Do not load new values. #0000 1 Load prescaler, modulus, and PWM values of the corresponding submodule. #0001 RUN Run 8 4 read-write 0 PWM generator is disabled in the corresponding submodule. #0000 1 PWM generator is enabled in the corresponding submodule. #0001 MCTRL1 Master Control Register 1 0x18A 16 read-write n 0x0 0x0 MONPLL Monitor PLL State 0 2 read-write 00 Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. #00 01 Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. #01 10 Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset. #10 11 Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset. #11 OUTEN Output Enable Register 0x180 16 read-write n 0x0 0x0 PWMA_EN PWM_A Output Enables 8 4 read-write 0 PWM_A output disabled. #0000 1 PWM_A output enabled. #0001 PWMB_EN PWM_B Output Enables 4 4 read-write 0 PWM_B output disabled. #0000 1 PWM_B output enabled. #0001 PWMX_EN PWM_X Output Enables 0 4 read-write 0 PWM_X output disabled. #0000 1 PWM_X output enabled. #0001 SM0CAPTCOMPA Capture Compare A Register 0x6C 16 read-write n 0x0 0x0 EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only SM0CAPTCOMPB Capture Compare B Register 0x74 16 read-write n 0x0 0x0 EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only SM0CAPTCOMPX Capture Compare X Register 0x7C 16 read-write n 0x0 0x0 EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only SM0CAPTCTRLA Capture Control A Register 0x68 16 read-write n 0x0 0x0 ARMA Arm A 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. #1 CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only CFAWM Capture A FIFOs Water Mark 8 2 read-write EDGA0 Edge A 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGA1 Edge A 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTA_EN Edge Counter A Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELA Input Select A 6 1 read-write 0 Raw PWM_A input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. #1 ONESHOTA One Shot Mode A 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. #1 SM0CAPTCTRLB Capture Control B Register 0x70 16 read-write n 0x0 0x0 ARMB Arm B 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. #1 CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only CFBWM Capture B FIFOs Water Mark 8 2 read-write EDGB0 Edge B 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGB1 Edge B 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTB_EN Edge Counter B Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELB Input Select B 6 1 read-write 0 Raw PWM_B input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. #1 ONESHOTB One Shot Mode B 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. #1 SM0CAPTCTRLX Capture Control X Register 0x78 16 read-write n 0x0 0x0 ARMX Arm X 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. #1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only EDGCNTX_EN Edge Counter X Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 EDGX0 Edge X 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGX1 Edge X 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 INP_SELX Input Select X 6 1 read-write 0 Raw PWM_X input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. #1 ONESHOTX One Shot Mode Aux 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. #1 SM0CNT Counter Register 0x0 16 read-only n 0x0 0x0 CNT Counter Register Bits 0 16 read-only SM0CTRL Control Register 0xC 16 read-write n 0x0 0x0 DBLEN Double Switching Enable 0 1 read-write 0 Double switching disabled. #0 1 Double switching enabled. #1 DBLX PWMX Double Switching Enable 1 1 read-write 0 PWMX double pulse disabled. #0 1 PWMX double pulse enabled. #1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write 0 Full-cycle reloads disabled. #0 1 Full-cycle reloads enabled. #1 HALF Half Cycle Reload 11 1 read-write 0 Half-cycle reloads disabled. #0 1 Half-cycle reloads enabled. #1 LDFQ Load Frequency 12 4 read-write 0000 Every PWM opportunity #0000 0001 Every 2 PWM opportunities #0001 0010 Every 3 PWM opportunities #0010 0011 Every 4 PWM opportunities #0011 0100 Every 5 PWM opportunities #0100 0101 Every 6 PWM opportunities #0101 0110 Every 7 PWM opportunities #0110 0111 Every 8 PWM opportunities #0111 1000 Every 9 PWM opportunities #1000 1001 Every 10 PWM opportunities #1001 1010 Every 11 PWM opportunities #1010 1011 Every 12 PWM opportunities #1011 1100 Every 13 PWM opportunities #1100 1101 Every 14 PWM opportunities #1101 1110 Every 15 PWM opportunities #1110 1111 Every 16 PWM opportunities #1111 LDMOD Load Mode Select 2 1 read-write 0 Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set. #0 1 Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. #1 PRSC Prescaler 4 3 read-write 000 PWM clock frequency = fclk #000 001 PWM clock frequency = fclk/2 #001 010 PWM clock frequency = fclk/4 #010 011 PWM clock frequency = fclk/8 #011 100 PWM clock frequency = fclk/16 #100 101 PWM clock frequency = fclk/32 #101 110 PWM clock frequency = fclk/64 #110 111 PWM clock frequency = fclk/128 #111 SM0CTRL2 Control 2 Register 0x8 16 read-write n 0x0 0x0 CLK_SEL Clock Source Select 0 2 read-write 00 The IPBus clock is used as the clock for the local prescaler and counter. #00 01 EXT_CLK is used as the clock for the local prescaler and counter. #01 10 Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. #10 DBGEN Debug Enable 15 1 read-write FORCE Force Initialization 6 1 write-only FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write 000 The local force signal, CTRL2[FORCE], from this submodule is used to force updates. #000 001 The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. #001 010 The local reload signal from this submodule is used to force updates without regard to the state of LDOK. #010 011 The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #011 100 The local sync signal from this submodule is used to force updates. #100 101 The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #101 110 The external force signal, EXT_FORCE, from outside the PWM module causes updates. #110 111 The external sync signal, EXT_SYNC, from outside the PWM module causes updates. #111 FRCEN This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by CTRL2[INIT_SEL] 7 1 read-write 0 Initialization from a FORCE_OUT is disabled. #0 1 Initialization from a FORCE_OUT is enabled. #1 INDEP Independent or Complementary Pair Operation 13 1 read-write 0 PWM_A and PWM_B form a complementary PWM pair. #0 1 PWM_A and PWM_B outputs are independent PWMs. #1 INIT_SEL Initialization Control Select 8 2 read-write 00 Local sync (PWM_X) causes initialization. #00 01 Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. #01 10 Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. #10 11 EXT_SYNC causes initialization. #11 PWM23_INIT PWM23 Initial Value 12 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWMX_INIT PWM_X Initial Value 10 1 read-write RELOAD_SEL Reload Source Select 2 1 read-write 0 The local RELOAD signal is used to reload registers. #0 1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. #1 WAITEN WAIT Enable 14 1 read-write SM0CVAL0 Capture Value 0 Register 0x80 16 read-only n 0x0 0x0 CAPTVAL0 This read-only register stores the value captured from the submodule counter 0 16 read-only SM0CVAL0CYC Capture Value 0 Cycle Register 0x84 16 read-only n 0x0 0x0 CVAL0CYC This read-only register stores the cycle number corresponding to the value captured in CVAL0 0 4 read-only SM0CVAL1 Capture Value 1 Register 0x88 16 read-only n 0x0 0x0 CAPTVAL1 This read-only register stores the value captured from the submodule counter 0 16 read-only SM0CVAL1CYC Capture Value 1 Cycle Register 0x8C 16 read-only n 0x0 0x0 CVAL1CYC This read-only register stores the cycle number corresponding to the value captured in CVAL1 0 4 read-only SM0CVAL2 Capture Value 2 Register 0x90 16 read-only n 0x0 0x0 CAPTVAL2 This read-only register stores the value captured from the submodule counter 0 16 read-only SM0CVAL2CYC Capture Value 2 Cycle Register 0x94 16 read-only n 0x0 0x0 CVAL2CYC This read-only register stores the cycle number corresponding to the value captured in CVAL2 0 4 read-only SM0CVAL3 Capture Value 3 Register 0x98 16 read-only n 0x0 0x0 CAPTVAL3 This read-only register stores the value captured from the submodule counter 0 16 read-only SM0CVAL3CYC Capture Value 3 Cycle Register 0x9C 16 read-only n 0x0 0x0 CVAL3CYC This read-only register stores the cycle number corresponding to the value captured in CVAL3 0 4 read-only SM0CVAL4 Capture Value 4 Register 0xA0 16 read-only n 0x0 0x0 CAPTVAL4 This read-only register stores the value captured from the submodule counter 0 16 read-only SM0CVAL4CYC Capture Value 4 Cycle Register 0xA4 16 read-only n 0x0 0x0 CVAL4CYC This read-only register stores the cycle number corresponding to the value captured in CVAL4 0 4 read-only SM0CVAL5 Capture Value 5 Register 0xA8 16 read-only n 0x0 0x0 CAPTVAL5 This read-only register stores the value captured from the submodule counter 0 16 read-only SM0CVAL5CYC Capture Value 5 Cycle Register 0xAC 16 read-only n 0x0 0x0 CVAL5CYC This read-only register stores the cycle number corresponding to the value captured in CVAL5 0 4 read-only SM0DISMAP0 Fault Disable Mapping Register 0 0x58 16 read-write n 0x0 0x0 DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write SM0DMAEN DMA Enable Register 0x50 16 read-write n 0x0 0x0 CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write 00 Read DMA requests disabled. #00 01 Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. #01 10 A local sync (VAL1 matches counter) sets the read DMA request. #10 11 A local reload (STS[RF] being set) sets the read DMA request. #11 CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write FAND FIFO Watermark AND Control 8 1 read-write 0 Selected FIFO watermarks are OR'ed together. #0 1 Selected FIFO watermarks are AND'ed together. #1 VALDE Value Registers DMA Enable 9 1 read-write 0 DMA write requests disabled #0 1 DMA write requests for the VALx and FRACVALx registers enabled #1 SM0DTCNT0 Deadtime Count Register 0 0x60 16 read-write n 0x0 0x0 DTCNT0 The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC23_EN] is set) 0 16 read-write SM0DTCNT1 Deadtime Count Register 1 0x64 16 read-write n 0x0 0x0 DTCNT1 The DTCNT1 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC45_EN] is set) 0 16 read-write SM0FRACVAL1 Fractional Value Register 1 0x18 16 read-write n 0x0 0x0 FRACVAL1 Fractional Value 1 Register 11 5 read-write SM0FRACVAL2 Fractional Value Register 2 0x20 16 read-write n 0x0 0x0 FRACVAL2 Fractional Value 2 11 5 read-write SM0FRACVAL3 Fractional Value Register 3 0x28 16 read-write n 0x0 0x0 FRACVAL3 Fractional Value 3 11 5 read-write SM0FRACVAL4 Fractional Value Register 4 0x30 16 read-write n 0x0 0x0 FRACVAL4 Fractional Value 4 11 5 read-write SM0FRACVAL5 Fractional Value Register 5 0x38 16 read-write n 0x0 0x0 FRACVAL5 Fractional Value 5 11 5 read-write SM0FRCTRL Fractional Control Register 0x40 16 read-write n 0x0 0x0 FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write 0 Disable fractional cycle length for the PWM period. #0 1 Enable fractional cycle length for the PWM period. #1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write 0 Disable fractional cycle placement for PWM_A. #0 1 Enable fractional cycle placement for PWM_A. #1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write 0 Disable fractional cycle placement for PWM_B. #0 1 Enable fractional cycle placement for PWM_B. #1 FRAC_PU Fractional Delay Circuit Power Up 8 1 read-write 0 Turn off fractional delay logic. #0 1 Power up fractional delay logic. #1 TEST Test Status Bit 15 1 read-only SM0INIT Initial Count Register 0x4 16 read-write n 0x0 0x0 INIT Initial Count Register Bits 0 16 read-write SM0INTEN Interrupt Enable Register 0x4C 16 read-write n 0x0 0x0 CA0IE Capture A 0 Interrupt Enable 10 1 read-write 0 Interrupt request disabled for STS[CFA0]. #0 1 Interrupt request enabled for STS[CFA0]. #1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write 0 Interrupt request disabled for STS[CFA1]. #0 1 Interrupt request enabled for STS[CFA1]. #1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write 0 Interrupt request disabled for STS[CFB0]. #0 1 Interrupt request enabled for STS[CFB0]. #1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write 0 Interrupt request disabled for STS[CFB1]. #0 1 Interrupt request enabled for STS[CFB1]. #1 CMPIE Compare Interrupt Enables 0 6 read-write 0 The corresponding STS[CMPF] bit will not cause an interrupt request. #0 1 The corresponding STS[CMPF] bit will cause an interrupt request. #1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write 0 Interrupt request disabled for STS[CFX0]. #0 1 Interrupt request enabled for STS[CFX0]. #1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write 0 Interrupt request disabled for STS[CFX1]. #0 1 Interrupt request enabled for STS[CFX1]. #1 REIE Reload Error Interrupt Enable 13 1 read-write 0 STS[REF] CPU interrupt requests disabled #0 1 STS[REF] CPU interrupt requests enabled #1 RIE Reload Interrupt Enable 12 1 read-write 0 STS[RF] CPU interrupt requests disabled #0 1 STS[RF] CPU interrupt requests enabled #1 SM0OCTRL Output Control Register 0x44 16 read-write n 0x0 0x0 POLA PWM_A Output Polarity 10 1 read-write 0 PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. #0 1 PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. #1 POLB PWM_B Output Polarity 9 1 read-write 0 PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. #0 1 PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. #1 POLX PWM_X Output Polarity 8 1 read-write 0 PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. #0 1 PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. #1 PWMAFS PWM_A Fault State 4 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMA_IN PWM_A Input 15 1 read-only PWMBFS PWM_B Fault State 2 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMB_IN PWM_B Input 14 1 read-only PWMXFS PWM_X Fault State 0 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMX_IN PWM_X Input 13 1 read-only SM0STS Status Register 0x48 16 read-write n 0x0 0x0 CFA0 Capture Flag A0 10 1 read-write CFA1 Capture Flag A1 11 1 read-write CFB0 Capture Flag B0 8 1 read-write CFB1 Capture Flag B1 9 1 read-write CFX0 Capture Flag X0 6 1 read-write CFX1 Capture Flag X1 7 1 read-write CMPF Compare Flags 0 6 read-write 0 No compare event has occurred for a particular VALx value. #0 1 A compare event has occurred for a particular VALx value. #1 REF Reload Error Flag 13 1 read-write 0 No reload error occurred. #0 1 Reload signal occurred with non-coherent data and MCTRL0[LDOK] = 0. #1 RF Reload Flag 12 1 read-write 0 No new reload cycle since last STS[RF] clearing #0 1 New reload cycle since last STS[RF] clearing #1 RUF Registers Updated Flag 14 1 read-only 0 No register update has occurred since last reload. #0 1 At least one of the double buffered registers has been updated since the last reload. #1 SM0TCTRL Output Trigger Control Register 0x54 16 read-write n 0x0 0x0 OUT_TRIG_EN Output Trigger Enables 0 6 read-write 0 PWM_OUT_TRIGx will not set when the counter value matches the VALx value. #0 1 PWM_OUT_TRIGx will set when the counter value matches the VALx value. #1 PWAOT0 Output Trigger 0 Source Select 15 1 read-write 0 Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. #0 1 Route the PWM0 output to the PWM_OUT_TRIG0 port. #1 PWBOT1 Output Trigger 1 Source Select 14 1 read-write 0 Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. #0 1 Route the PWM1 output to the PWM_OUT_TRIG1 port. #1 TRGFRQ Trigger frequency 12 1 read-write 0 Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #0 1 Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #1 SM0VAL0 Value Register 0 0x14 16 read-write n 0x0 0x0 VAL0 Value Register 0 0 16 read-write SM0VAL1 Value Register 1 0x1C 16 read-write n 0x0 0x0 VAL1 Value Register 1 0 16 read-write SM0VAL2 Value Register 2 0x24 16 read-write n 0x0 0x0 VAL2 Value Register 2 0 16 read-write SM0VAL3 Value Register 3 0x2C 16 read-write n 0x0 0x0 VAL3 Value Register 3 0 16 read-write SM0VAL4 Value Register 4 0x34 16 read-write n 0x0 0x0 VAL4 Value Register 4 0 16 read-write SM0VAL5 Value Register 5 0x3C 16 read-write n 0x0 0x0 VAL5 Value Register 5 0 16 read-write SM1CAPTCOMPA Capture Compare A Register 0x102 16 read-write n 0x0 0x0 EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only SM1CAPTCOMPB Capture Compare B Register 0x10E 16 read-write n 0x0 0x0 EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only SM1CAPTCOMPX Capture Compare X Register 0x11A 16 read-write n 0x0 0x0 EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only SM1CAPTCTRLA Capture Control A Register 0xFC 16 read-write n 0x0 0x0 ARMA Arm A 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. #1 CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only CFAWM Capture A FIFOs Water Mark 8 2 read-write EDGA0 Edge A 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGA1 Edge A 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTA_EN Edge Counter A Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELA Input Select A 6 1 read-write 0 Raw PWM_A input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. #1 ONESHOTA One Shot Mode A 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. #1 SM1CAPTCTRLB Capture Control B Register 0x108 16 read-write n 0x0 0x0 ARMB Arm B 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. #1 CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only CFBWM Capture B FIFOs Water Mark 8 2 read-write EDGB0 Edge B 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGB1 Edge B 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTB_EN Edge Counter B Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELB Input Select B 6 1 read-write 0 Raw PWM_B input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. #1 ONESHOTB One Shot Mode B 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. #1 SM1CAPTCTRLX Capture Control X Register 0x114 16 read-write n 0x0 0x0 ARMX Arm X 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. #1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only EDGCNTX_EN Edge Counter X Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 EDGX0 Edge X 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGX1 Edge X 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 INP_SELX Input Select X 6 1 read-write 0 Raw PWM_X input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. #1 ONESHOTX One Shot Mode Aux 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. #1 SM1CNT Counter Register 0x60 16 read-only n 0x0 0x0 CNT Counter Register Bits 0 16 read-only SM1CTRL Control Register 0x72 16 read-write n 0x0 0x0 DBLEN Double Switching Enable 0 1 read-write 0 Double switching disabled. #0 1 Double switching enabled. #1 DBLX PWMX Double Switching Enable 1 1 read-write 0 PWMX double pulse disabled. #0 1 PWMX double pulse enabled. #1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write 0 Full-cycle reloads disabled. #0 1 Full-cycle reloads enabled. #1 HALF Half Cycle Reload 11 1 read-write 0 Half-cycle reloads disabled. #0 1 Half-cycle reloads enabled. #1 LDFQ Load Frequency 12 4 read-write 0000 Every PWM opportunity #0000 0001 Every 2 PWM opportunities #0001 0010 Every 3 PWM opportunities #0010 0011 Every 4 PWM opportunities #0011 0100 Every 5 PWM opportunities #0100 0101 Every 6 PWM opportunities #0101 0110 Every 7 PWM opportunities #0110 0111 Every 8 PWM opportunities #0111 1000 Every 9 PWM opportunities #1000 1001 Every 10 PWM opportunities #1001 1010 Every 11 PWM opportunities #1010 1011 Every 12 PWM opportunities #1011 1100 Every 13 PWM opportunities #1100 1101 Every 14 PWM opportunities #1101 1110 Every 15 PWM opportunities #1110 1111 Every 16 PWM opportunities #1111 LDMOD Load Mode Select 2 1 read-write 0 Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set. #0 1 Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. #1 PRSC Prescaler 4 3 read-write 000 PWM clock frequency = fclk #000 001 PWM clock frequency = fclk/2 #001 010 PWM clock frequency = fclk/4 #010 011 PWM clock frequency = fclk/8 #011 100 PWM clock frequency = fclk/16 #100 101 PWM clock frequency = fclk/32 #101 110 PWM clock frequency = fclk/64 #110 111 PWM clock frequency = fclk/128 #111 SM1CTRL2 Control 2 Register 0x6C 16 read-write n 0x0 0x0 CLK_SEL Clock Source Select 0 2 read-write 00 The IPBus clock is used as the clock for the local prescaler and counter. #00 01 EXT_CLK is used as the clock for the local prescaler and counter. #01 10 Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. #10 DBGEN Debug Enable 15 1 read-write FORCE Force Initialization 6 1 write-only FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write 000 The local force signal, CTRL2[FORCE], from this submodule is used to force updates. #000 001 The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. #001 010 The local reload signal from this submodule is used to force updates without regard to the state of LDOK. #010 011 The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #011 100 The local sync signal from this submodule is used to force updates. #100 101 The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #101 110 The external force signal, EXT_FORCE, from outside the PWM module causes updates. #110 111 The external sync signal, EXT_SYNC, from outside the PWM module causes updates. #111 FRCEN This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by CTRL2[INIT_SEL] 7 1 read-write 0 Initialization from a FORCE_OUT is disabled. #0 1 Initialization from a FORCE_OUT is enabled. #1 INDEP Independent or Complementary Pair Operation 13 1 read-write 0 PWM_A and PWM_B form a complementary PWM pair. #0 1 PWM_A and PWM_B outputs are independent PWMs. #1 INIT_SEL Initialization Control Select 8 2 read-write 00 Local sync (PWM_X) causes initialization. #00 01 Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. #01 10 Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. #10 11 EXT_SYNC causes initialization. #11 PWM23_INIT PWM23 Initial Value 12 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWMX_INIT PWM_X Initial Value 10 1 read-write RELOAD_SEL Reload Source Select 2 1 read-write 0 The local RELOAD signal is used to reload registers. #0 1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. #1 WAITEN WAIT Enable 14 1 read-write SM1CVAL0 Capture Value 0 Register 0x120 16 read-only n 0x0 0x0 CAPTVAL0 This read-only register stores the value captured from the submodule counter 0 16 read-only SM1CVAL0CYC Capture Value 0 Cycle Register 0x126 16 read-only n 0x0 0x0 CVAL0CYC This read-only register stores the cycle number corresponding to the value captured in CVAL0 0 4 read-only SM1CVAL1 Capture Value 1 Register 0x12C 16 read-only n 0x0 0x0 CAPTVAL1 This read-only register stores the value captured from the submodule counter 0 16 read-only SM1CVAL1CYC Capture Value 1 Cycle Register 0x132 16 read-only n 0x0 0x0 CVAL1CYC This read-only register stores the cycle number corresponding to the value captured in CVAL1 0 4 read-only SM1CVAL2 Capture Value 2 Register 0x138 16 read-only n 0x0 0x0 CAPTVAL2 This read-only register stores the value captured from the submodule counter 0 16 read-only SM1CVAL2CYC Capture Value 2 Cycle Register 0x13E 16 read-only n 0x0 0x0 CVAL2CYC This read-only register stores the cycle number corresponding to the value captured in CVAL2 0 4 read-only SM1CVAL3 Capture Value 3 Register 0x144 16 read-only n 0x0 0x0 CAPTVAL3 This read-only register stores the value captured from the submodule counter 0 16 read-only SM1CVAL3CYC Capture Value 3 Cycle Register 0x14A 16 read-only n 0x0 0x0 CVAL3CYC This read-only register stores the cycle number corresponding to the value captured in CVAL3 0 4 read-only SM1CVAL4 Capture Value 4 Register 0x150 16 read-only n 0x0 0x0 CAPTVAL4 This read-only register stores the value captured from the submodule counter 0 16 read-only SM1CVAL4CYC Capture Value 4 Cycle Register 0x156 16 read-only n 0x0 0x0 CVAL4CYC This read-only register stores the cycle number corresponding to the value captured in CVAL4 0 4 read-only SM1CVAL5 Capture Value 5 Register 0x15C 16 read-only n 0x0 0x0 CAPTVAL5 This read-only register stores the value captured from the submodule counter 0 16 read-only SM1CVAL5CYC Capture Value 5 Cycle Register 0x162 16 read-only n 0x0 0x0 CVAL5CYC This read-only register stores the cycle number corresponding to the value captured in CVAL5 0 4 read-only SM1DISMAP0 Fault Disable Mapping Register 0 0xE4 16 read-write n 0x0 0x0 DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write SM1DMAEN DMA Enable Register 0xD8 16 read-write n 0x0 0x0 CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write 00 Read DMA requests disabled. #00 01 Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. #01 10 A local sync (VAL1 matches counter) sets the read DMA request. #10 11 A local reload (STS[RF] being set) sets the read DMA request. #11 CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write FAND FIFO Watermark AND Control 8 1 read-write 0 Selected FIFO watermarks are OR'ed together. #0 1 Selected FIFO watermarks are AND'ed together. #1 VALDE Value Registers DMA Enable 9 1 read-write 0 DMA write requests disabled #0 1 DMA write requests for the VALx and FRACVALx registers enabled #1 SM1DTCNT0 Deadtime Count Register 0 0xF0 16 read-write n 0x0 0x0 DTCNT0 The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC23_EN] is set) 0 16 read-write SM1DTCNT1 Deadtime Count Register 1 0xF6 16 read-write n 0x0 0x0 DTCNT1 The DTCNT1 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC45_EN] is set) 0 16 read-write SM1FRACVAL1 Fractional Value Register 1 0x84 16 read-write n 0x0 0x0 FRACVAL1 Fractional Value 1 Register 11 5 read-write SM1FRACVAL2 Fractional Value Register 2 0x90 16 read-write n 0x0 0x0 FRACVAL2 Fractional Value 2 11 5 read-write SM1FRACVAL3 Fractional Value Register 3 0x9C 16 read-write n 0x0 0x0 FRACVAL3 Fractional Value 3 11 5 read-write SM1FRACVAL4 Fractional Value Register 4 0xA8 16 read-write n 0x0 0x0 FRACVAL4 Fractional Value 4 11 5 read-write SM1FRACVAL5 Fractional Value Register 5 0xB4 16 read-write n 0x0 0x0 FRACVAL5 Fractional Value 5 11 5 read-write SM1FRCTRL Fractional Control Register 0xC0 16 read-write n 0x0 0x0 FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write 0 Disable fractional cycle length for the PWM period. #0 1 Enable fractional cycle length for the PWM period. #1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write 0 Disable fractional cycle placement for PWM_A. #0 1 Enable fractional cycle placement for PWM_A. #1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write 0 Disable fractional cycle placement for PWM_B. #0 1 Enable fractional cycle placement for PWM_B. #1 FRAC_PU Fractional Delay Circuit Power Up 8 1 read-write 0 Turn off fractional delay logic. #0 1 Power up fractional delay logic. #1 TEST Test Status Bit 15 1 read-only SM1INIT Initial Count Register 0x66 16 read-write n 0x0 0x0 INIT Initial Count Register Bits 0 16 read-write SM1INTEN Interrupt Enable Register 0xD2 16 read-write n 0x0 0x0 CA0IE Capture A 0 Interrupt Enable 10 1 read-write 0 Interrupt request disabled for STS[CFA0]. #0 1 Interrupt request enabled for STS[CFA0]. #1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write 0 Interrupt request disabled for STS[CFA1]. #0 1 Interrupt request enabled for STS[CFA1]. #1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write 0 Interrupt request disabled for STS[CFB0]. #0 1 Interrupt request enabled for STS[CFB0]. #1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write 0 Interrupt request disabled for STS[CFB1]. #0 1 Interrupt request enabled for STS[CFB1]. #1 CMPIE Compare Interrupt Enables 0 6 read-write 0 The corresponding STS[CMPF] bit will not cause an interrupt request. #0 1 The corresponding STS[CMPF] bit will cause an interrupt request. #1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write 0 Interrupt request disabled for STS[CFX0]. #0 1 Interrupt request enabled for STS[CFX0]. #1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write 0 Interrupt request disabled for STS[CFX1]. #0 1 Interrupt request enabled for STS[CFX1]. #1 REIE Reload Error Interrupt Enable 13 1 read-write 0 STS[REF] CPU interrupt requests disabled #0 1 STS[REF] CPU interrupt requests enabled #1 RIE Reload Interrupt Enable 12 1 read-write 0 STS[RF] CPU interrupt requests disabled #0 1 STS[RF] CPU interrupt requests enabled #1 SM1OCTRL Output Control Register 0xC6 16 read-write n 0x0 0x0 POLA PWM_A Output Polarity 10 1 read-write 0 PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. #0 1 PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. #1 POLB PWM_B Output Polarity 9 1 read-write 0 PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. #0 1 PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. #1 POLX PWM_X Output Polarity 8 1 read-write 0 PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. #0 1 PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. #1 PWMAFS PWM_A Fault State 4 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMA_IN PWM_A Input 15 1 read-only PWMBFS PWM_B Fault State 2 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMB_IN PWM_B Input 14 1 read-only PWMXFS PWM_X Fault State 0 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMX_IN PWM_X Input 13 1 read-only SM1STS Status Register 0xCC 16 read-write n 0x0 0x0 CFA0 Capture Flag A0 10 1 read-write CFA1 Capture Flag A1 11 1 read-write CFB0 Capture Flag B0 8 1 read-write CFB1 Capture Flag B1 9 1 read-write CFX0 Capture Flag X0 6 1 read-write CFX1 Capture Flag X1 7 1 read-write CMPF Compare Flags 0 6 read-write 0 No compare event has occurred for a particular VALx value. #0 1 A compare event has occurred for a particular VALx value. #1 REF Reload Error Flag 13 1 read-write 0 No reload error occurred. #0 1 Reload signal occurred with non-coherent data and MCTRL0[LDOK] = 0. #1 RF Reload Flag 12 1 read-write 0 No new reload cycle since last STS[RF] clearing #0 1 New reload cycle since last STS[RF] clearing #1 RUF Registers Updated Flag 14 1 read-only 0 No register update has occurred since last reload. #0 1 At least one of the double buffered registers has been updated since the last reload. #1 SM1TCTRL Output Trigger Control Register 0xDE 16 read-write n 0x0 0x0 OUT_TRIG_EN Output Trigger Enables 0 6 read-write 0 PWM_OUT_TRIGx will not set when the counter value matches the VALx value. #0 1 PWM_OUT_TRIGx will set when the counter value matches the VALx value. #1 PWAOT0 Output Trigger 0 Source Select 15 1 read-write 0 Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. #0 1 Route the PWM0 output to the PWM_OUT_TRIG0 port. #1 PWBOT1 Output Trigger 1 Source Select 14 1 read-write 0 Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. #0 1 Route the PWM1 output to the PWM_OUT_TRIG1 port. #1 TRGFRQ Trigger frequency 12 1 read-write 0 Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #0 1 Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #1 SM1VAL0 Value Register 0 0x7E 16 read-write n 0x0 0x0 VAL0 Value Register 0 0 16 read-write SM1VAL1 Value Register 1 0x8A 16 read-write n 0x0 0x0 VAL1 Value Register 1 0 16 read-write SM1VAL2 Value Register 2 0x96 16 read-write n 0x0 0x0 VAL2 Value Register 2 0 16 read-write SM1VAL3 Value Register 3 0xA2 16 read-write n 0x0 0x0 VAL3 Value Register 3 0 16 read-write SM1VAL4 Value Register 4 0xAE 16 read-write n 0x0 0x0 VAL4 Value Register 4 0 16 read-write SM1VAL5 Value Register 5 0xBA 16 read-write n 0x0 0x0 VAL5 Value Register 5 0 16 read-write SM2CAPTCOMPA Capture Compare A Register 0x1F8 16 read-write n 0x0 0x0 EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only SM2CAPTCOMPB Capture Compare B Register 0x208 16 read-write n 0x0 0x0 EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only SM2CAPTCOMPX Capture Compare X Register 0x218 16 read-write n 0x0 0x0 EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only SM2CAPTCTRLA Capture Control A Register 0x1F0 16 read-write n 0x0 0x0 ARMA Arm A 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. #1 CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only CFAWM Capture A FIFOs Water Mark 8 2 read-write EDGA0 Edge A 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGA1 Edge A 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTA_EN Edge Counter A Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELA Input Select A 6 1 read-write 0 Raw PWM_A input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. #1 ONESHOTA One Shot Mode A 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. #1 SM2CAPTCTRLB Capture Control B Register 0x200 16 read-write n 0x0 0x0 ARMB Arm B 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. #1 CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only CFBWM Capture B FIFOs Water Mark 8 2 read-write EDGB0 Edge B 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGB1 Edge B 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTB_EN Edge Counter B Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELB Input Select B 6 1 read-write 0 Raw PWM_B input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. #1 ONESHOTB One Shot Mode B 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. #1 SM2CAPTCTRLX Capture Control X Register 0x210 16 read-write n 0x0 0x0 ARMX Arm X 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. #1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only EDGCNTX_EN Edge Counter X Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 EDGX0 Edge X 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGX1 Edge X 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 INP_SELX Input Select X 6 1 read-write 0 Raw PWM_X input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. #1 ONESHOTX One Shot Mode Aux 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. #1 SM2CNT Counter Register 0x120 16 read-only n 0x0 0x0 CNT Counter Register Bits 0 16 read-only SM2CTRL Control Register 0x138 16 read-write n 0x0 0x0 DBLEN Double Switching Enable 0 1 read-write 0 Double switching disabled. #0 1 Double switching enabled. #1 DBLX PWMX Double Switching Enable 1 1 read-write 0 PWMX double pulse disabled. #0 1 PWMX double pulse enabled. #1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write 0 Full-cycle reloads disabled. #0 1 Full-cycle reloads enabled. #1 HALF Half Cycle Reload 11 1 read-write 0 Half-cycle reloads disabled. #0 1 Half-cycle reloads enabled. #1 LDFQ Load Frequency 12 4 read-write 0000 Every PWM opportunity #0000 0001 Every 2 PWM opportunities #0001 0010 Every 3 PWM opportunities #0010 0011 Every 4 PWM opportunities #0011 0100 Every 5 PWM opportunities #0100 0101 Every 6 PWM opportunities #0101 0110 Every 7 PWM opportunities #0110 0111 Every 8 PWM opportunities #0111 1000 Every 9 PWM opportunities #1000 1001 Every 10 PWM opportunities #1001 1010 Every 11 PWM opportunities #1010 1011 Every 12 PWM opportunities #1011 1100 Every 13 PWM opportunities #1100 1101 Every 14 PWM opportunities #1101 1110 Every 15 PWM opportunities #1110 1111 Every 16 PWM opportunities #1111 LDMOD Load Mode Select 2 1 read-write 0 Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set. #0 1 Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. #1 PRSC Prescaler 4 3 read-write 000 PWM clock frequency = fclk #000 001 PWM clock frequency = fclk/2 #001 010 PWM clock frequency = fclk/4 #010 011 PWM clock frequency = fclk/8 #011 100 PWM clock frequency = fclk/16 #100 101 PWM clock frequency = fclk/32 #101 110 PWM clock frequency = fclk/64 #110 111 PWM clock frequency = fclk/128 #111 SM2CTRL2 Control 2 Register 0x130 16 read-write n 0x0 0x0 CLK_SEL Clock Source Select 0 2 read-write 00 The IPBus clock is used as the clock for the local prescaler and counter. #00 01 EXT_CLK is used as the clock for the local prescaler and counter. #01 10 Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. #10 DBGEN Debug Enable 15 1 read-write FORCE Force Initialization 6 1 write-only FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write 000 The local force signal, CTRL2[FORCE], from this submodule is used to force updates. #000 001 The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. #001 010 The local reload signal from this submodule is used to force updates without regard to the state of LDOK. #010 011 The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #011 100 The local sync signal from this submodule is used to force updates. #100 101 The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #101 110 The external force signal, EXT_FORCE, from outside the PWM module causes updates. #110 111 The external sync signal, EXT_SYNC, from outside the PWM module causes updates. #111 FRCEN This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by CTRL2[INIT_SEL] 7 1 read-write 0 Initialization from a FORCE_OUT is disabled. #0 1 Initialization from a FORCE_OUT is enabled. #1 INDEP Independent or Complementary Pair Operation 13 1 read-write 0 PWM_A and PWM_B form a complementary PWM pair. #0 1 PWM_A and PWM_B outputs are independent PWMs. #1 INIT_SEL Initialization Control Select 8 2 read-write 00 Local sync (PWM_X) causes initialization. #00 01 Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. #01 10 Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. #10 11 EXT_SYNC causes initialization. #11 PWM23_INIT PWM23 Initial Value 12 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWMX_INIT PWM_X Initial Value 10 1 read-write RELOAD_SEL Reload Source Select 2 1 read-write 0 The local RELOAD signal is used to reload registers. #0 1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. #1 WAITEN WAIT Enable 14 1 read-write SM2CVAL0 Capture Value 0 Register 0x220 16 read-only n 0x0 0x0 CAPTVAL0 This read-only register stores the value captured from the submodule counter 0 16 read-only SM2CVAL0CYC Capture Value 0 Cycle Register 0x228 16 read-only n 0x0 0x0 CVAL0CYC This read-only register stores the cycle number corresponding to the value captured in CVAL0 0 4 read-only SM2CVAL1 Capture Value 1 Register 0x230 16 read-only n 0x0 0x0 CAPTVAL1 This read-only register stores the value captured from the submodule counter 0 16 read-only SM2CVAL1CYC Capture Value 1 Cycle Register 0x238 16 read-only n 0x0 0x0 CVAL1CYC This read-only register stores the cycle number corresponding to the value captured in CVAL1 0 4 read-only SM2CVAL2 Capture Value 2 Register 0x240 16 read-only n 0x0 0x0 CAPTVAL2 This read-only register stores the value captured from the submodule counter 0 16 read-only SM2CVAL2CYC Capture Value 2 Cycle Register 0x248 16 read-only n 0x0 0x0 CVAL2CYC This read-only register stores the cycle number corresponding to the value captured in CVAL2 0 4 read-only SM2CVAL3 Capture Value 3 Register 0x250 16 read-only n 0x0 0x0 CAPTVAL3 This read-only register stores the value captured from the submodule counter 0 16 read-only SM2CVAL3CYC Capture Value 3 Cycle Register 0x258 16 read-only n 0x0 0x0 CVAL3CYC This read-only register stores the cycle number corresponding to the value captured in CVAL3 0 4 read-only SM2CVAL4 Capture Value 4 Register 0x260 16 read-only n 0x0 0x0 CAPTVAL4 This read-only register stores the value captured from the submodule counter 0 16 read-only SM2CVAL4CYC Capture Value 4 Cycle Register 0x268 16 read-only n 0x0 0x0 CVAL4CYC This read-only register stores the cycle number corresponding to the value captured in CVAL4 0 4 read-only SM2CVAL5 Capture Value 5 Register 0x270 16 read-only n 0x0 0x0 CAPTVAL5 This read-only register stores the value captured from the submodule counter 0 16 read-only SM2CVAL5CYC Capture Value 5 Cycle Register 0x278 16 read-only n 0x0 0x0 CVAL5CYC This read-only register stores the cycle number corresponding to the value captured in CVAL5 0 4 read-only SM2DISMAP0 Fault Disable Mapping Register 0 0x1D0 16 read-write n 0x0 0x0 DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write SM2DMAEN DMA Enable Register 0x1C0 16 read-write n 0x0 0x0 CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write 00 Read DMA requests disabled. #00 01 Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. #01 10 A local sync (VAL1 matches counter) sets the read DMA request. #10 11 A local reload (STS[RF] being set) sets the read DMA request. #11 CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write FAND FIFO Watermark AND Control 8 1 read-write 0 Selected FIFO watermarks are OR'ed together. #0 1 Selected FIFO watermarks are AND'ed together. #1 VALDE Value Registers DMA Enable 9 1 read-write 0 DMA write requests disabled #0 1 DMA write requests for the VALx and FRACVALx registers enabled #1 SM2DTCNT0 Deadtime Count Register 0 0x1E0 16 read-write n 0x0 0x0 DTCNT0 The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC23_EN] is set) 0 16 read-write SM2DTCNT1 Deadtime Count Register 1 0x1E8 16 read-write n 0x0 0x0 DTCNT1 The DTCNT1 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC45_EN] is set) 0 16 read-write SM2FRACVAL1 Fractional Value Register 1 0x150 16 read-write n 0x0 0x0 FRACVAL1 Fractional Value 1 Register 11 5 read-write SM2FRACVAL2 Fractional Value Register 2 0x160 16 read-write n 0x0 0x0 FRACVAL2 Fractional Value 2 11 5 read-write SM2FRACVAL3 Fractional Value Register 3 0x170 16 read-write n 0x0 0x0 FRACVAL3 Fractional Value 3 11 5 read-write SM2FRACVAL4 Fractional Value Register 4 0x180 16 read-write n 0x0 0x0 FRACVAL4 Fractional Value 4 11 5 read-write SM2FRACVAL5 Fractional Value Register 5 0x190 16 read-write n 0x0 0x0 FRACVAL5 Fractional Value 5 11 5 read-write SM2FRCTRL Fractional Control Register 0x1A0 16 read-write n 0x0 0x0 FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write 0 Disable fractional cycle length for the PWM period. #0 1 Enable fractional cycle length for the PWM period. #1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write 0 Disable fractional cycle placement for PWM_A. #0 1 Enable fractional cycle placement for PWM_A. #1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write 0 Disable fractional cycle placement for PWM_B. #0 1 Enable fractional cycle placement for PWM_B. #1 FRAC_PU Fractional Delay Circuit Power Up 8 1 read-write 0 Turn off fractional delay logic. #0 1 Power up fractional delay logic. #1 TEST Test Status Bit 15 1 read-only SM2INIT Initial Count Register 0x128 16 read-write n 0x0 0x0 INIT Initial Count Register Bits 0 16 read-write SM2INTEN Interrupt Enable Register 0x1B8 16 read-write n 0x0 0x0 CA0IE Capture A 0 Interrupt Enable 10 1 read-write 0 Interrupt request disabled for STS[CFA0]. #0 1 Interrupt request enabled for STS[CFA0]. #1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write 0 Interrupt request disabled for STS[CFA1]. #0 1 Interrupt request enabled for STS[CFA1]. #1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write 0 Interrupt request disabled for STS[CFB0]. #0 1 Interrupt request enabled for STS[CFB0]. #1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write 0 Interrupt request disabled for STS[CFB1]. #0 1 Interrupt request enabled for STS[CFB1]. #1 CMPIE Compare Interrupt Enables 0 6 read-write 0 The corresponding STS[CMPF] bit will not cause an interrupt request. #0 1 The corresponding STS[CMPF] bit will cause an interrupt request. #1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write 0 Interrupt request disabled for STS[CFX0]. #0 1 Interrupt request enabled for STS[CFX0]. #1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write 0 Interrupt request disabled for STS[CFX1]. #0 1 Interrupt request enabled for STS[CFX1]. #1 REIE Reload Error Interrupt Enable 13 1 read-write 0 STS[REF] CPU interrupt requests disabled #0 1 STS[REF] CPU interrupt requests enabled #1 RIE Reload Interrupt Enable 12 1 read-write 0 STS[RF] CPU interrupt requests disabled #0 1 STS[RF] CPU interrupt requests enabled #1 SM2OCTRL Output Control Register 0x1A8 16 read-write n 0x0 0x0 POLA PWM_A Output Polarity 10 1 read-write 0 PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. #0 1 PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. #1 POLB PWM_B Output Polarity 9 1 read-write 0 PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. #0 1 PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. #1 POLX PWM_X Output Polarity 8 1 read-write 0 PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. #0 1 PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. #1 PWMAFS PWM_A Fault State 4 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMA_IN PWM_A Input 15 1 read-only PWMBFS PWM_B Fault State 2 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMB_IN PWM_B Input 14 1 read-only PWMXFS PWM_X Fault State 0 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMX_IN PWM_X Input 13 1 read-only SM2STS Status Register 0x1B0 16 read-write n 0x0 0x0 CFA0 Capture Flag A0 10 1 read-write CFA1 Capture Flag A1 11 1 read-write CFB0 Capture Flag B0 8 1 read-write CFB1 Capture Flag B1 9 1 read-write CFX0 Capture Flag X0 6 1 read-write CFX1 Capture Flag X1 7 1 read-write CMPF Compare Flags 0 6 read-write 0 No compare event has occurred for a particular VALx value. #0 1 A compare event has occurred for a particular VALx value. #1 REF Reload Error Flag 13 1 read-write 0 No reload error occurred. #0 1 Reload signal occurred with non-coherent data and MCTRL0[LDOK] = 0. #1 RF Reload Flag 12 1 read-write 0 No new reload cycle since last STS[RF] clearing #0 1 New reload cycle since last STS[RF] clearing #1 RUF Registers Updated Flag 14 1 read-only 0 No register update has occurred since last reload. #0 1 At least one of the double buffered registers has been updated since the last reload. #1 SM2TCTRL Output Trigger Control Register 0x1C8 16 read-write n 0x0 0x0 OUT_TRIG_EN Output Trigger Enables 0 6 read-write 0 PWM_OUT_TRIGx will not set when the counter value matches the VALx value. #0 1 PWM_OUT_TRIGx will set when the counter value matches the VALx value. #1 PWAOT0 Output Trigger 0 Source Select 15 1 read-write 0 Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. #0 1 Route the PWM0 output to the PWM_OUT_TRIG0 port. #1 PWBOT1 Output Trigger 1 Source Select 14 1 read-write 0 Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. #0 1 Route the PWM1 output to the PWM_OUT_TRIG1 port. #1 TRGFRQ Trigger frequency 12 1 read-write 0 Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #0 1 Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #1 SM2VAL0 Value Register 0 0x148 16 read-write n 0x0 0x0 VAL0 Value Register 0 0 16 read-write SM2VAL1 Value Register 1 0x158 16 read-write n 0x0 0x0 VAL1 Value Register 1 0 16 read-write SM2VAL2 Value Register 2 0x168 16 read-write n 0x0 0x0 VAL2 Value Register 2 0 16 read-write SM2VAL3 Value Register 3 0x178 16 read-write n 0x0 0x0 VAL3 Value Register 3 0 16 read-write SM2VAL4 Value Register 4 0x188 16 read-write n 0x0 0x0 VAL4 Value Register 4 0 16 read-write SM2VAL5 Value Register 5 0x198 16 read-write n 0x0 0x0 VAL5 Value Register 5 0 16 read-write SM3CAPTCOMPA Capture Compare A Register 0x34E 16 read-write n 0x0 0x0 EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only SM3CAPTCOMPB Capture Compare B Register 0x362 16 read-write n 0x0 0x0 EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only SM3CAPTCOMPX Capture Compare X Register 0x376 16 read-write n 0x0 0x0 EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only SM3CAPTCTRLA Capture Control A Register 0x344 16 read-write n 0x0 0x0 ARMA Arm A 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. #1 CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only CFAWM Capture A FIFOs Water Mark 8 2 read-write EDGA0 Edge A 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGA1 Edge A 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTA_EN Edge Counter A Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELA Input Select A 6 1 read-write 0 Raw PWM_A input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. #1 ONESHOTA One Shot Mode A 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. #1 SM3CAPTCTRLB Capture Control B Register 0x358 16 read-write n 0x0 0x0 ARMB Arm B 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. #1 CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only CFBWM Capture B FIFOs Water Mark 8 2 read-write EDGB0 Edge B 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGB1 Edge B 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGCNTB_EN Edge Counter B Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 INP_SELB Input Select B 6 1 read-write 0 Raw PWM_B input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. #1 ONESHOTB One Shot Mode B 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. #1 SM3CAPTCTRLX Capture Control X Register 0x36C 16 read-write n 0x0 0x0 ARMX Arm X 0 1 read-write 0 Input capture operation is disabled. #0 1 Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. #1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only EDGCNTX_EN Edge Counter X Enable 7 1 read-write 0 Edge counter disabled and held in reset #0 1 Edge counter enabled #1 EDGX0 Edge X 0 2 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 EDGX1 Edge X 1 4 2 read-write 00 Disabled #00 01 Capture falling edges #01 10 Capture rising edges #10 11 Capture any edge #11 INP_SELX Input Select X 6 1 read-write 0 Raw PWM_X input signal selected as source. #0 1 Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. #1 ONESHOTX One Shot Mode Aux 1 1 read-write 0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. #0 1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. #1 SM3CNT Counter Register 0x240 16 read-only n 0x0 0x0 CNT Counter Register Bits 0 16 read-only SM3CTRL Control Register 0x25E 16 read-write n 0x0 0x0 DBLEN Double Switching Enable 0 1 read-write 0 Double switching disabled. #0 1 Double switching enabled. #1 DBLX PWMX Double Switching Enable 1 1 read-write 0 PWMX double pulse disabled. #0 1 PWMX double pulse enabled. #1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write 0 Full-cycle reloads disabled. #0 1 Full-cycle reloads enabled. #1 HALF Half Cycle Reload 11 1 read-write 0 Half-cycle reloads disabled. #0 1 Half-cycle reloads enabled. #1 LDFQ Load Frequency 12 4 read-write 0000 Every PWM opportunity #0000 0001 Every 2 PWM opportunities #0001 0010 Every 3 PWM opportunities #0010 0011 Every 4 PWM opportunities #0011 0100 Every 5 PWM opportunities #0100 0101 Every 6 PWM opportunities #0101 0110 Every 7 PWM opportunities #0110 0111 Every 8 PWM opportunities #0111 1000 Every 9 PWM opportunities #1000 1001 Every 10 PWM opportunities #1001 1010 Every 11 PWM opportunities #1010 1011 Every 12 PWM opportunities #1011 1100 Every 13 PWM opportunities #1100 1101 Every 14 PWM opportunities #1101 1110 Every 15 PWM opportunities #1110 1111 Every 16 PWM opportunities #1111 LDMOD Load Mode Select 2 1 read-write 0 Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set. #0 1 Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. #1 PRSC Prescaler 4 3 read-write 000 PWM clock frequency = fclk #000 001 PWM clock frequency = fclk/2 #001 010 PWM clock frequency = fclk/4 #010 011 PWM clock frequency = fclk/8 #011 100 PWM clock frequency = fclk/16 #100 101 PWM clock frequency = fclk/32 #101 110 PWM clock frequency = fclk/64 #110 111 PWM clock frequency = fclk/128 #111 SM3CTRL2 Control 2 Register 0x254 16 read-write n 0x0 0x0 CLK_SEL Clock Source Select 0 2 read-write 00 The IPBus clock is used as the clock for the local prescaler and counter. #00 01 EXT_CLK is used as the clock for the local prescaler and counter. #01 10 Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. #10 DBGEN Debug Enable 15 1 read-write FORCE Force Initialization 6 1 write-only FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write 000 The local force signal, CTRL2[FORCE], from this submodule is used to force updates. #000 001 The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. #001 010 The local reload signal from this submodule is used to force updates without regard to the state of LDOK. #010 011 The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #011 100 The local sync signal from this submodule is used to force updates. #100 101 The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. #101 110 The external force signal, EXT_FORCE, from outside the PWM module causes updates. #110 111 The external sync signal, EXT_SYNC, from outside the PWM module causes updates. #111 FRCEN This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by CTRL2[INIT_SEL] 7 1 read-write 0 Initialization from a FORCE_OUT is disabled. #0 1 Initialization from a FORCE_OUT is enabled. #1 INDEP Independent or Complementary Pair Operation 13 1 read-write 0 PWM_A and PWM_B form a complementary PWM pair. #0 1 PWM_A and PWM_B outputs are independent PWMs. #1 INIT_SEL Initialization Control Select 8 2 read-write 00 Local sync (PWM_X) causes initialization. #00 01 Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. #01 10 Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. #10 11 EXT_SYNC causes initialization. #11 PWM23_INIT PWM23 Initial Value 12 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWMX_INIT PWM_X Initial Value 10 1 read-write RELOAD_SEL Reload Source Select 2 1 read-write 0 The local RELOAD signal is used to reload registers. #0 1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. #1 WAITEN WAIT Enable 14 1 read-write SM3CVAL0 Capture Value 0 Register 0x380 16 read-only n 0x0 0x0 CAPTVAL0 This read-only register stores the value captured from the submodule counter 0 16 read-only SM3CVAL0CYC Capture Value 0 Cycle Register 0x38A 16 read-only n 0x0 0x0 CVAL0CYC This read-only register stores the cycle number corresponding to the value captured in CVAL0 0 4 read-only SM3CVAL1 Capture Value 1 Register 0x394 16 read-only n 0x0 0x0 CAPTVAL1 This read-only register stores the value captured from the submodule counter 0 16 read-only SM3CVAL1CYC Capture Value 1 Cycle Register 0x39E 16 read-only n 0x0 0x0 CVAL1CYC This read-only register stores the cycle number corresponding to the value captured in CVAL1 0 4 read-only SM3CVAL2 Capture Value 2 Register 0x3A8 16 read-only n 0x0 0x0 CAPTVAL2 This read-only register stores the value captured from the submodule counter 0 16 read-only SM3CVAL2CYC Capture Value 2 Cycle Register 0x3B2 16 read-only n 0x0 0x0 CVAL2CYC This read-only register stores the cycle number corresponding to the value captured in CVAL2 0 4 read-only SM3CVAL3 Capture Value 3 Register 0x3BC 16 read-only n 0x0 0x0 CAPTVAL3 This read-only register stores the value captured from the submodule counter 0 16 read-only SM3CVAL3CYC Capture Value 3 Cycle Register 0x3C6 16 read-only n 0x0 0x0 CVAL3CYC This read-only register stores the cycle number corresponding to the value captured in CVAL3 0 4 read-only SM3CVAL4 Capture Value 4 Register 0x3D0 16 read-only n 0x0 0x0 CAPTVAL4 This read-only register stores the value captured from the submodule counter 0 16 read-only SM3CVAL4CYC Capture Value 4 Cycle Register 0x3DA 16 read-only n 0x0 0x0 CVAL4CYC This read-only register stores the cycle number corresponding to the value captured in CVAL4 0 4 read-only SM3CVAL5 Capture Value 5 Register 0x3E4 16 read-only n 0x0 0x0 CAPTVAL5 This read-only register stores the value captured from the submodule counter 0 16 read-only SM3CVAL5CYC Capture Value 5 Cycle Register 0x3EE 16 read-only n 0x0 0x0 CVAL5CYC This read-only register stores the cycle number corresponding to the value captured in CVAL5 0 4 read-only SM3DISMAP0 Fault Disable Mapping Register 0 0x31C 16 read-write n 0x0 0x0 DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write SM3DMAEN DMA Enable Register 0x308 16 read-write n 0x0 0x0 CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write 00 Read DMA requests disabled. #00 01 Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. #01 10 A local sync (VAL1 matches counter) sets the read DMA request. #10 11 A local reload (STS[RF] being set) sets the read DMA request. #11 CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write FAND FIFO Watermark AND Control 8 1 read-write 0 Selected FIFO watermarks are OR'ed together. #0 1 Selected FIFO watermarks are AND'ed together. #1 VALDE Value Registers DMA Enable 9 1 read-write 0 DMA write requests disabled #0 1 DMA write requests for the VALx and FRACVALx registers enabled #1 SM3DTCNT0 Deadtime Count Register 0 0x330 16 read-write n 0x0 0x0 DTCNT0 The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC23_EN] is set) 0 16 read-write SM3DTCNT1 Deadtime Count Register 1 0x33A 16 read-write n 0x0 0x0 DTCNT1 The DTCNT1 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC45_EN] is set) 0 16 read-write SM3FRACVAL1 Fractional Value Register 1 0x27C 16 read-write n 0x0 0x0 FRACVAL1 Fractional Value 1 Register 11 5 read-write SM3FRACVAL2 Fractional Value Register 2 0x290 16 read-write n 0x0 0x0 FRACVAL2 Fractional Value 2 11 5 read-write SM3FRACVAL3 Fractional Value Register 3 0x2A4 16 read-write n 0x0 0x0 FRACVAL3 Fractional Value 3 11 5 read-write SM3FRACVAL4 Fractional Value Register 4 0x2B8 16 read-write n 0x0 0x0 FRACVAL4 Fractional Value 4 11 5 read-write SM3FRACVAL5 Fractional Value Register 5 0x2CC 16 read-write n 0x0 0x0 FRACVAL5 Fractional Value 5 11 5 read-write SM3FRCTRL Fractional Control Register 0x2E0 16 read-write n 0x0 0x0 FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write 0 Disable fractional cycle length for the PWM period. #0 1 Enable fractional cycle length for the PWM period. #1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write 0 Disable fractional cycle placement for PWM_A. #0 1 Enable fractional cycle placement for PWM_A. #1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write 0 Disable fractional cycle placement for PWM_B. #0 1 Enable fractional cycle placement for PWM_B. #1 FRAC_PU Fractional Delay Circuit Power Up 8 1 read-write 0 Turn off fractional delay logic. #0 1 Power up fractional delay logic. #1 TEST Test Status Bit 15 1 read-only SM3INIT Initial Count Register 0x24A 16 read-write n 0x0 0x0 INIT Initial Count Register Bits 0 16 read-write SM3INTEN Interrupt Enable Register 0x2FE 16 read-write n 0x0 0x0 CA0IE Capture A 0 Interrupt Enable 10 1 read-write 0 Interrupt request disabled for STS[CFA0]. #0 1 Interrupt request enabled for STS[CFA0]. #1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write 0 Interrupt request disabled for STS[CFA1]. #0 1 Interrupt request enabled for STS[CFA1]. #1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write 0 Interrupt request disabled for STS[CFB0]. #0 1 Interrupt request enabled for STS[CFB0]. #1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write 0 Interrupt request disabled for STS[CFB1]. #0 1 Interrupt request enabled for STS[CFB1]. #1 CMPIE Compare Interrupt Enables 0 6 read-write 0 The corresponding STS[CMPF] bit will not cause an interrupt request. #0 1 The corresponding STS[CMPF] bit will cause an interrupt request. #1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write 0 Interrupt request disabled for STS[CFX0]. #0 1 Interrupt request enabled for STS[CFX0]. #1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write 0 Interrupt request disabled for STS[CFX1]. #0 1 Interrupt request enabled for STS[CFX1]. #1 REIE Reload Error Interrupt Enable 13 1 read-write 0 STS[REF] CPU interrupt requests disabled #0 1 STS[REF] CPU interrupt requests enabled #1 RIE Reload Interrupt Enable 12 1 read-write 0 STS[RF] CPU interrupt requests disabled #0 1 STS[RF] CPU interrupt requests enabled #1 SM3OCTRL Output Control Register 0x2EA 16 read-write n 0x0 0x0 POLA PWM_A Output Polarity 10 1 read-write 0 PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. #0 1 PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. #1 POLB PWM_B Output Polarity 9 1 read-write 0 PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. #0 1 PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. #1 POLX PWM_X Output Polarity 8 1 read-write 0 PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. #0 1 PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. #1 PWMAFS PWM_A Fault State 4 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMA_IN PWM_A Input 15 1 read-only PWMBFS PWM_B Fault State 2 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMB_IN PWM_B Input 14 1 read-only PWMXFS PWM_X Fault State 0 2 read-write 00 Output is forced to logic 0 state prior to consideration of output polarity control. #00 01 Output is forced to logic 1 state prior to consideration of output polarity control. #01 10 Output is tristated. #10 11 Output is tristated. #11 PWMX_IN PWM_X Input 13 1 read-only SM3STS Status Register 0x2F4 16 read-write n 0x0 0x0 CFA0 Capture Flag A0 10 1 read-write CFA1 Capture Flag A1 11 1 read-write CFB0 Capture Flag B0 8 1 read-write CFB1 Capture Flag B1 9 1 read-write CFX0 Capture Flag X0 6 1 read-write CFX1 Capture Flag X1 7 1 read-write CMPF Compare Flags 0 6 read-write 0 No compare event has occurred for a particular VALx value. #0 1 A compare event has occurred for a particular VALx value. #1 REF Reload Error Flag 13 1 read-write 0 No reload error occurred. #0 1 Reload signal occurred with non-coherent data and MCTRL0[LDOK] = 0. #1 RF Reload Flag 12 1 read-write 0 No new reload cycle since last STS[RF] clearing #0 1 New reload cycle since last STS[RF] clearing #1 RUF Registers Updated Flag 14 1 read-only 0 No register update has occurred since last reload. #0 1 At least one of the double buffered registers has been updated since the last reload. #1 SM3TCTRL Output Trigger Control Register 0x312 16 read-write n 0x0 0x0 OUT_TRIG_EN Output Trigger Enables 0 6 read-write 0 PWM_OUT_TRIGx will not set when the counter value matches the VALx value. #0 1 PWM_OUT_TRIGx will set when the counter value matches the VALx value. #1 PWAOT0 Output Trigger 0 Source Select 15 1 read-write 0 Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. #0 1 Route the PWM0 output to the PWM_OUT_TRIG0 port. #1 PWBOT1 Output Trigger 1 Source Select 14 1 read-write 0 Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. #0 1 Route the PWM1 output to the PWM_OUT_TRIG1 port. #1 TRGFRQ Trigger frequency 12 1 read-write 0 Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #0 1 Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. #1 SM3VAL0 Value Register 0 0x272 16 read-write n 0x0 0x0 VAL0 Value Register 0 0 16 read-write SM3VAL1 Value Register 1 0x286 16 read-write n 0x0 0x0 VAL1 Value Register 1 0 16 read-write SM3VAL2 Value Register 2 0x29A 16 read-write n 0x0 0x0 VAL2 Value Register 2 0 16 read-write SM3VAL3 Value Register 3 0x2AE 16 read-write n 0x0 0x0 VAL3 Value Register 3 0 16 read-write SM3VAL4 Value Register 4 0x2C2 16 read-write n 0x0 0x0 VAL4 Value Register 4 0 16 read-write SM3VAL5 Value Register 5 0x2D6 16 read-write n 0x0 0x0 VAL5 Value Register 5 0 16 read-write SWCOUT Software Controlled Output Register 0x184 16 read-write n 0x0 0x0 SM0OUT23 Submodule 0 Software Controlled Output 23 1 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. #0 1 A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. #1 SM0OUT45 Submodule 0 Software Controlled Output 45 0 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. #0 1 A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. #1 SM1OUT23 Submodule 1 Software Controlled Output 23 3 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. #0 1 A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. #1 SM1OUT45 Submodule 1 Software Controlled Output 45 2 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. #0 1 A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. #1 SM2OUT23 Submodule 2 Software Controlled Output 23 5 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. #0 1 A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. #1 SM2OUT45 Submodule 2 Software Controlled Output 45 4 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. #0 1 A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. #1 SM3OUT23 Submodule 3 Software Controlled Output 23 7 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. #0 1 A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. #1 SM3OUT45 Submodule 3 Software Controlled Output 45 6 1 read-write 0 A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. #0 1 A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. #1 RCM Reset Control Module RCM 0x0 0x0 0xA registers n RPFC Reset Pin Filter Control register 0x4 8 read-write n 0x0 0x0 RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes 0 2 read-write 00 All filtering disabled #00 01 Bus clock filter enabled for normal operation #01 10 LPO clock filter enabled for normal operation #10 RSTFLTSS Reset Pin Filter Select in Stop Mode 2 1 read-write 0 All filtering disabled #0 1 LPO clock filter enabled #1 RPFW Reset Pin Filter Width register 0x5 8 read-write n 0x0 0x0 RSTFLTSEL Reset Pin Filter Bus Clock Select 0 5 read-write 00000 Bus clock filter count is 1 #00000 00001 Bus clock filter count is 2 #00001 00010 Bus clock filter count is 3 #00010 00011 Bus clock filter count is 4 #00011 00100 Bus clock filter count is 5 #00100 00101 Bus clock filter count is 6 #00101 00110 Bus clock filter count is 7 #00110 00111 Bus clock filter count is 8 #00111 01000 Bus clock filter count is 9 #01000 01001 Bus clock filter count is 10 #01001 01010 Bus clock filter count is 11 #01010 01011 Bus clock filter count is 12 #01011 01100 Bus clock filter count is 13 #01100 01101 Bus clock filter count is 14 #01101 01110 Bus clock filter count is 15 #01110 01111 Bus clock filter count is 16 #01111 10000 Bus clock filter count is 17 #10000 10001 Bus clock filter count is 18 #10001 10010 Bus clock filter count is 19 #10010 10011 Bus clock filter count is 20 #10011 10100 Bus clock filter count is 21 #10100 10101 Bus clock filter count is 22 #10101 10110 Bus clock filter count is 23 #10110 10111 Bus clock filter count is 24 #10111 11000 Bus clock filter count is 25 #11000 11001 Bus clock filter count is 26 #11001 11010 Bus clock filter count is 27 #11010 11011 Bus clock filter count is 28 #11011 11100 Bus clock filter count is 29 #11100 11101 Bus clock filter count is 30 #11101 11110 Bus clock filter count is 31 #11110 11111 Bus clock filter count is 32 #11111 SRS0 System Reset Status Register 0 0x0 8 read-only n 0x0 0x0 LOC Loss-of-Clock Reset 2 1 read-only 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 LOL Loss-of-Lock Reset 3 1 read-only 0 Reset not caused by a loss of lock in the PLL #0 1 Reset caused by a loss of lock in the PLL #1 LVD Low-Voltage Detect Reset 1 1 read-only 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 PIN External Reset Pin 6 1 read-only 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 POR Power-On Reset 7 1 read-only 0 Reset not caused by POR #0 1 Reset caused by POR #1 WAKEUP Low Leakage Wakeup Reset 0 1 read-only 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 WDOG Watchdog 5 1 read-only 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 SRS1 System Reset Status Register 1 0x1 8 read-only n 0x0 0x0 JTAG JTAG Generated Reset 0 1 read-only 0 Reset not caused by JTAG #0 1 Reset caused by JTAG #1 LOCKUP Core Lockup 1 1 read-only 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 MDM_AP MDM-AP System Reset Request 3 1 read-only 0 Reset not caused by host debugger system setting of the System Reset Request bit #0 1 Reset caused by host debugger system setting of the System Reset Request bit #1 SACKERR Stop Mode Acknowledge Error Reset 5 1 read-only 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 SW Software 2 1 read-only 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 SSRS0 Sticky System Reset Status Register 0 0x8 8 read-write n 0x0 0x0 SLOC Sticky Loss-of-Clock Reset 2 1 read-write 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 SLOL Sticky Loss-of-Lock Reset 3 1 read-write 0 Reset not caused by a loss of lock in the PLL #0 1 Reset caused by a loss of lock in the PLL #1 SLVD Sticky Low-Voltage Detect Reset 1 1 read-write 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 SPIN Sticky External Reset Pin 6 1 read-write 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 SPOR Sticky Power-On Reset 7 1 read-write 0 Reset not caused by POR #0 1 Reset caused by POR #1 SWAKEUP Sticky Low Leakage Wakeup Reset 0 1 read-write 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 SWDOG Sticky Watchdog 5 1 read-write 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 SSRS1 Sticky System Reset Status Register 1 0x9 8 read-write n 0x0 0x0 SJTAG Sticky JTAG Generated Reset 0 1 read-write 0 Reset not caused by JTAG #0 1 Reset caused by JTAG #1 SLOCKUP Sticky Core Lockup 1 1 read-write 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 SMDM_AP Sticky MDM-AP System Reset Request 3 1 read-write 0 Reset not caused by host debugger system setting of the System Reset Request bit #0 1 Reset caused by host debugger system setting of the System Reset Request bit #1 SSACKERR Sticky Stop Mode Acknowledge Error Reset 5 1 read-write 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 SSW Sticky Software 2 1 read-write 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 RFSYS System register file RFSYS 0x0 0x0 0x20 registers n REG0 Register file register 0x0 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG1 Register file register 0x4 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG2 Register file register 0xC 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG3 Register file register 0x18 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG4 Register file register 0x28 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG5 Register file register 0x3C 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG6 Register file register 0x54 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG7 Register file register 0x70 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write RFVBAT VBAT register file RFVBAT 0x0 0x0 0x20 registers n REG0 VBAT register file register 0x0 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG1 VBAT register file register 0x4 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG2 VBAT register file register 0xC 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG3 VBAT register file register 0x18 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG4 VBAT register file register 0x28 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG5 VBAT register file register 0x3C 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG6 VBAT register file register 0x54 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG7 VBAT register file register 0x70 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write SIM System Integration Module SIM 0x0 0x0 0x110C registers n ADCOPT ADC Additional Option Register 0x1108 32 read-write n 0x0 0x0 ADC0ALTTRGEN ADC0 alternate trigger enable 22 2 read-write 00 XBARA output 39. #00 01 PDB0 channel1 trigger selected for ADC0 #01 10 PDB1 channel0 trigger selected for ADC0 #10 11 Alternate trigger selected for ADC0 as defined by ADC0TRGSEL. #11 ADC0PRETRGSEL ADC0 pretrigger select 20 1 read-write 0 Pre-trigger A #0 1 Pre-trigger B #1 ADC0TRGSEL ADC0 trigger select 16 4 read-write 0000 PDB0 external trigger pin input (PDB0_EXTRG) #0000 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0011 High speed comparator 2 output #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 XBARA output 38 #1100 1110 Low-power timer (LPTMR) trigger #1110 HSADCIRCLK HSADC Clock Status 25 1 read-only 0 HSADC clock is Core/System clock. #0 1 HSADC clock is MCGIRCLK. #1 HSADCSTOPEN Enable HSADCs in STOP mode 26 1 read-write 0 HSADCs stopsin system STOP modes #0 1 HSADCs can be enabled in system STOP modes #1 CLKDIV1 System Clock Divider Register 1 0x1044 32 read-write n 0x0 0x0 OUTDIV1 Clock 1 output divider value 28 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV2 Clock 2 output divider value 24 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV3 Clock 3 output divider value 20 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV4 Clock 4 output divider value 16 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 CLKDIV4 System Clock Divider Register 4 0x1068 32 read-write n 0x0 0x0 TRACEDIV Trace clock divider divisor 1 3 read-write TRACEDIVEN Debug Trace Divider Control 28 1 read-write 0 Debug trace divider disabled #0 1 Debug trace divider enabled #1 TRACEFRAC Trace clock divider fraction 0 1 read-write FCFG1 Flash Configuration Register 1 0x104C 32 read-write n 0x0 0x0 FLASHDIS Flash Disable 0 1 read-write 0 Flash is enabled #0 1 Flash is disabled #1 FLASHDOZE Flash Doze 1 1 read-write 0 Flash remains enabled during Wait mode #0 1 Flash is disabled for the duration of Wait mode #1 PFSIZE Program flash size 24 4 read-only 1011 512 KB of program flash memory #1011 1101 1024 KB of program flash memory #1101 FCFG2 Flash Configuration Register 2 0x1050 32 read-only n 0x0 0x0 MAXADDR0 Max address block 0 24 7 read-only MISCTRL0 Miscellaneous Control Register 0 0x106C 32 read-write n 0x0 0x0 CMPWIN0SRC CMP Sample/Window Input 0 Source 8 2 read-write 00 XBARA output 16. #00 01 CMP0 Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 0. #01 10 PDB0 pluse-out channel 0. #10 11 PDB1 pluse-out channel 0. #11 CMPWIN1SRC CMP Sample/Window Input 1 Source 10 2 read-write 00 XBARA output 17. #00 01 CMP1 Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 1. #01 10 PDB0 pluse-out channel 1. #10 11 PDB1 pluse-out channel 1. #11 CMPWIN2SRC CMP Sample/Window Input 2 Source 12 2 read-write 00 XBARA output 18. #00 01 CMP2 Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 2. #01 10 PDB0 pluse-out channel 2. #10 11 PDB1 pluse-out channel 2. #11 CMPWIN3SRC CMP Sample/Window Input 3 Source 14 2 read-write 00 XBARA output 19. #00 01 CMP3 Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 3. #01 10 PDB0 pluse-out channel 3. #10 11 PDB1 pluse-out channel 3. #11 DACTRIGSRC DAC0 Hardware Trigger Input Source 18 2 read-write 00 XBARA output 15. #00 01 DAC0 can be triggered by both PDB0 interval trigger 0 and PDB1 interval trigger 0. #01 10 PDB0 interval trigger 0 #10 11 PDB1 interval trigger 0 #11 EWMINSRC EWM_IN Source 16 1 read-write 0 XBARA output 58. #0 1 EWM_IN pin #1 MISCTRL1 Miscellaneous Control Register 1 0x1070 32 read-write n 0x0 0x0 SYNCCMP0SAMPLEWIN Synchronize XBARA's output for CMP0's Sample/Window Input with flash/slow clock 20 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCCMP1SAMPLEWIN Synchronize XBARA's output for CMP1's Sample/Window Input with flash/slow clock 21 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCCMP2SAMPLEWIN Synchronize XBARA's output for CMP2's Sample/Window Input with flash/slow clock 22 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCCMP3SAMPLEWIN Synchronize XBARA's output for CMP3's Sample/Window Input with flash/slow clock 23 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCDACHWTRIG Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock 16 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCEWMIN Synchronize XBARA's output for EWM's ewm_in with flash/slow clock 17 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCXBARAPITTRIG0 Synchronize XBARA's Input PIT Trigger 0 with fast clock 8 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCXBARAPITTRIG1 Synchronize XBARA's Input PIT Trigger 1 with fast clock 9 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCXBARAPITTRIG2 Synchronize XBARA's Input PIT Trigger 2 with fast clock 10 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCXBARAPITTRIG3 Synchronize XBARA's Input PIT Trigger 3 with fast clock 11 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCXBARBPITTRIG0 Synchronize XBARB's Input PIT Trigger 0 with fast clock 12 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 SYNCXBARBPITTRIG1 Synchronize XBARB's Input PIT Trigger 1 with fast clock 13 1 read-write 0 Disable, bypass synchronizer. #0 1 Enable. #1 PWRC Power Control Register 0x1104 32 read-write n 0x0 0x0 SR12STDBY Nanoedge Regulator 1.2 V Supply Standby Control 6 2 read-write 00 Nanoedge regulator 1.2 V supply placed in normal mode #00 01 Nanoedge regulator 1.2 V supply placed in standby mode. #01 10 Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until chip reset. #10 11 Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until chip reset. #11 SR27STDBY Nanoedge Regulator 2.7 V Supply Standby Control 2 2 read-write 00 Nanoedge regulator 2.7 V placed in normal mode. #00 01 Nanoedge regulator 2.7 V placed in standby mode. #01 10 Nanoedge regulator 2.7 V supply placed in normal mode and SR27STDBY is write protected until chip reset. #10 11 Nanoedge regulator 2.7 V supply placed in standby mode and SR27STDBY is write protected until chip reset. #11 SRPDN Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control 0 2 read-write 00 Nanoedge regulator placed in normal mode. #00 01 Nanoedge regulator placed in powerdown mode. #01 10 Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset. #10 11 Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset. #11 SRPWRDETEN Nanoedge PMC POWER Dectect Enable 8 1 read-write 0 Disable #0 1 Enable #1 SRPWROK Nanoedge PMC Status 16 1 read-only 0 Power supply for nanoedge isn't ready. #0 1 Power supply for nanoedge is OK. #1 SRPWRRDY Nanoedge PMC POWER Ready 9 1 read-write 0 Not ready #0 1 Assert PMC power output ready #1 SCGC1 System Clock Gating Control Register 1 0x1028 32 read-write n 0x0 0x0 PWM1_SM0 PWM1 submodule 0 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PWM1_SM1 PWM1 submodule 1 Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PWM1_SM2 PWM1 submodule 2 Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PWM1_SM3 PWM1 submodule 3 Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART4 UART4 Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART5 UART5 Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC2 System Clock Gating Control Register 2 0x102C 32 read-write n 0x0 0x0 ENET ENET Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 HSADC1 HSADC1 Clock Gate Control 28 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC3 System Clock Gating Control Register 3 0x1030 32 read-write n 0x0 0x0 FLEXCAN2 FlexCAN2 Clock Gate Control 4 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI2 SPI2 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 TRNG TRNG Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC4 System Clock Gating Control Register 4 0x1034 32 read-write n 0x0 0x0 CMP Comparators Clock Gate Control 19 1 read-write 0 Clock disabled #0 1 Clock enabled #1 EWM EWM Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C0 I2C0 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 I2C1 I2C1 Clock Gate Control 7 1 read-write PWM0_SM0 PWM0 submodule 0 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PWM0_SM1 PWM0 submodule 1 Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PWM0_SM2 PWM0 submodule 2 Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PWM0_SM3 PWM0 submodule 3 Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART0 UART0 Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART1 UART1 Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART2 UART2 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 UART3 UART3 Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC5 System Clock Gating Control Register 5 0x1038 32 read-write n 0x0 0x0 AOI AOI Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 ENC This bit controls the clock gate to the ENC module. 21 1 read-write 0 Clock disabled #0 1 Clock enabled #1 HSADC0 HSADC0 Clock Gate Control 28 1 read-write 0 Clock disabled #0 1 Clock enabled #1 LPTMR Low Power Timer Access Control 0 1 read-write 0 Access disabled #0 1 Access enabled #1 PORTA Port A Clock Gate Control 9 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTB Port B Clock Gate Control 10 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTC Port C Clock Gate Control 11 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTD Port D Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PORTE Port E Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 XBARA XBARA Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 XBARB XBARB Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC6 System Clock Gating Control Register 6 0x103C 32 read-write n 0x0 0x0 ADC0 ADC0 Clock Gate Control 27 1 read-write 0 Clock disabled #0 1 Clock enabled #1 CRC CRC Clock Gate Control 18 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DAC0 DAC0 Clock Gate Control 31 1 read-write 0 Clock disabled #0 1 Clock enabled #1 DMAMUX DMA Mux Clock Gate Control 1 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FLEXCAN0 FlexCAN0 Clock Gate Control 4 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FLEXCAN1 FlexCAN1 Clock Gate Control 5 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTF Flash Memory Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM0 FTM0 Clock Gate Control 24 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM1 FTM1 Clock Gate Control 25 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM2 FTM2 Clock Gate Control 26 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FTM3 FTM3 Clock Gate Control 6 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PDB0 PDB0 Clock Gate Control 22 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PDB1 PDB1 Clock Gate Control 17 1 read-write 0 Clock disabled #0 1 Clock enabled #1 PIT PIT Clock Gate Control 23 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI0 SPI0 Clock Gate Control 12 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SPI1 SPI1 Clock Gate Control 13 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SCGC7 System Clock Gating Control Register 7 0x1040 32 read-write n 0x0 0x0 DMA DMA Clock Gate Control 8 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FLEXBUS FlexBus Clock Gate Control 0 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SMPU SMPU Clock Gate Control 2 1 read-write 0 Clock disabled #0 1 Clock enabled #1 SDID System Device Identification Register 0x1024 32 read-only n 0x0 0x0 DIEID Device die number 7 5 read-only 00011 KV5x #00011 FAMILYID Kinetis Family ID 28 4 read-only 0101 This is the KV5x series #0101 PINID Pincount identification 0 4 read-only 1000 100-pin #1000 1010 144-pin #1010 REVID Device revision number 12 4 read-only SERIESID Kinetis Series ID 20 4 read-only 0110 Kinetis V series #0110 SUBFAMID Kinetis Sub-Family ID 24 4 read-only 0110 KVx6 Subfamily (eFlexPWM with FlexTimer and HSADC) #0110 1000 KVx8 Subfamily (eFlexPWM with FlexTimer, HSADC, and Ethernet) #1000 SOPT1 System Options Register 1 0x0 32 read-write n 0x0 0x0 OSC32KSEL 32K oscillator clock select 18 2 read-write 00 System oscillator (OSC32KCLK) #00 11 LPO 1 kHz #11 RAMSIZE RAM size 12 4 read-only 1001 128 KB #1001 1011 256 KB #1011 SOPT2 System Options Register 2 0x1004 32 read-write n 0x0 0x0 CLKOUTSEL CLKOUT select 5 3 read-write 000 FlexBus CLKOUT #000 010 Flash clock #010 011 LPO clock (1 kHz) #011 100 MCGIRCLK #100 101 OSCERCLK_UNDIV #101 110 OSCERCLK #110 FBSL FlexBus security level 8 2 read-write 00 All off-chip accesses (instruction and data) via the FlexBus are disallowed. #00 01 All off-chip accesses (instruction and data) via the FlexBus are disallowed. #01 10 Off-chip instruction accesses are disallowed. Data accesses are allowed. #10 11 Off-chip instruction accesses and data accesses are allowed. #11 PLLFLLSEL PLL/FLL clock select 16 2 read-write 00 MCGFLLCLK clock #00 01 MCGPLLCLK clock #01 RMIISRC RMII clock source select 19 1 read-write 0 EXTAL clock #0 1 External bypass clock (ENET_1588_CLKIN). #1 TIMESRC IEEE 1588 timestamp clock source select 20 2 read-write 00 Core/system clock #00 01 MCGFLLCLK , or MCGPLLCLK as selected by SOPT2[PLLFLLSEL]. #01 10 OSCERCLK clock #10 11 External bypass clock (ENET_1588_CLKIN) #11 TRACECLKSEL Debug trace clock select 12 1 read-write 0 MCGOUTCLK #0 1 Core/system clock #1 SOPT4 System Options Register 4 0x100C 32 read-write n 0x0 0x0 FTM0FLT0 FTM0 Fault 0 Select 0 1 read-write 0 FTM0_FLT0 pin #0 1 CMP0 out #1 FTM0FLT1 FTM0 Fault 1 Select 1 1 read-write 0 FTM0_FLT1 pin #0 1 CMP1 out #1 FTM0FLT2 FTM0 Fault 2 Select 2 1 read-write 0 FTM0_FLT2 pin #0 1 CMP2 out #1 FTM0FLT3 Selects the source of FTM0 fault 3 3 1 read-write 0 FTM0_FLT3 pin #0 1 XBARA output 49 #1 FTM0TRG0SRC FlexTimer 0 Hardware Trigger 0 Source Select 16 1 read-write 0 CMP0 output drives FTM0 hardware trigger 0 #0 1 FTM1 channel match drives FTM0 hardware trigger 0 #1 FTM0TRG1SRC FlexTimer 0 Hardware Trigger 1 Source Select 17 1 read-write 0 PDB0 channel 1 output trigger drives FTM0 hardware trigger 1 #0 1 FTM1 channel match drives FTM0 hardware trigger 1 #1 FTM0TRG2SRC FlexTimer 0 Hardware Trigger 2 Source Select 18 1 read-write 0 FTM0_FLT0 pin drives FTM0 hardware trigger 2 #0 1 XBARA output 34 drives FTM0 hardware trigger 2 #1 FTM1FLT0 FTM1 Fault 0 Select 4 1 read-write 0 FTM1_FLT0 pin #0 1 CMP0 out #1 FTM1TRG0SRC FlexTimer 1 Hardware Trigger 0 Source Select 20 1 read-write 0 CMP0 output drives FTM1 hardware trigger 0 #0 1 FTM0 channel match drives FTM1 hardware trigger 0 #1 FTM1TRG2SRC FlexTimer 1 Hardware Trigger 2 Source Select 22 1 read-write 0 FTM1_FLT0 pin drives FTM1 hardware trigger 2 #0 1 XBARA output 35 drives FTM1 hardware trigger 2 #1 FTM2FLT0 FTM2 Fault 0 Select 8 1 read-write 0 FTM2_FLT0 pin #0 1 CMP0 out #1 FTM2TRG0SRC FlexTimer 2 Hardware Trigger 0 Source Select 24 1 read-write 0 CMP0 output drives FTM2 hardware trigger 0 #0 1 FTM0 channel match drives FTM2 hardware trigger 0 #1 FTM2TRG2SRC FlexTimer 2 Hardware Trigger 2 Source Select 26 1 read-write 0 FTM2_FLT0 pin drives FTM2 hardware trigger 2 #0 1 XBARA output 36 drives FTM2 hardware trigger 2 #1 FTM3FLT0 FTM3 Fault 0 Select 12 1 read-write 0 FTM3_FLT0 pin #0 1 CMP0 out #1 FTM3TRG0SRC FlexTimer 3 Hardware Trigger 0 Source Select 28 1 read-write 0 CMP0 output drives FTM3 hardware trigger 0 #0 1 FTM1 channel match drives FTM3 hardware trigger 0 #1 FTM3TRG1SRC FlexTimer 3 Hardware Trigger 1 Source Select 29 1 read-write 0 PDB1 channel 1 output trigger drives FTM3 hardware trigger 1 #0 1 FTM1 channel match drives FTM3 hardware trigger 1 #1 FTM3TRG2SRC FlexTimer 3 Hardware Trigger 2 Source Select 30 1 read-write 0 FTM3_FLT0 pin drives FTM3 hardware trigger 2 #0 1 XBARA output 37 drives FTM3 hardware trigger 2 #1 SOPT5 System Options Register 5 0x1010 32 read-write n 0x0 0x0 UART0RXSRC UART 0 receive data source select 2 2 read-write 00 UART0_RX pin #00 01 CMP0 #01 10 CMP1 #10 UART0TXSRC UART 0 transmit data source select 0 2 read-write 00 UART0_TX pin #00 01 UART0_TX pin modulated with FTM1 channel 0 output #01 10 UART0_TX pin modulated with FTM2 channel 0 output #10 UART1RXSRC UART 1 receive data source select 6 2 read-write 00 UART1_RX pin #00 01 CMP0 #01 10 CMP1 #10 UART1TXSRC UART 1 transmit data source select 4 2 read-write 00 UART1_TX pin #00 01 UART1_TX pin modulated with FTM1 channel 0 output #01 10 UART1_TX pin modulated with FTM2 channel 0 output #10 SOPT7 System Options Register 7 0x1018 32 read-write n 0x0 0x0 HSADC0AALTTRGEN HSADC0A alternate trigger enable 6 2 read-write 00 XBARA output 12. #00 01 PDB0 channel0 trigger selected for HSADC0A. #01 HSADC0ATRGSEL HSADC0A trigger select 0 4 read-write 0000 PDB external trigger pin input (PDB0_EXTRG) #0000 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0011 High speed comparator 2 output #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 XBARA output 38 #1100 1110 Low-power timer trigger #1110 HSADC0BALTTRGEN HSADC0B alternate trigger enable 14 2 read-write 00 XBARA output 13. #00 01 PDB1 channel0 trigger selected for HSADC0B #01 HSADC0BTRGSEL HSADC0B trigger select 8 4 read-write 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0011 High speed comparator 2 output #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 XBARA output 41 #1100 1110 Low-power timer trigger #1110 HSADC1AALTTRGEN HSADC1A alternate trigger enable 22 2 read-write 00 XBARA output 42. #00 01 PDB1 channel 1 trigger selected for HSADC1A. #01 HSADC1ATRGSEL HSADC1A trigger select 16 4 read-write 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0011 High speed comparator 2 output #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 XBARA output 41 #1100 1110 Low-power timer trigger #1110 HSADC1BALTTRGEN HSADC1B alternate trigger enable 30 2 read-write 00 XBARA output 43. #00 01 PDB0 channel 1 trigger selected for HSADC1B #01 HSADC1BTRGSEL HSADC1B trigger select 24 4 read-write 0000 PDB external trigger pin input (PDB0_EXTRG) #0000 0001 High speed comparator 0 output #0001 0010 High speed comparator 1 output #0010 0011 High speed comparator 2 output #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 XBARA output 38 #1100 1110 Low-power timer trigger #1110 SOPT8 System Options Register 8 0x101C 32 read-write n 0x0 0x0 FTM0CFSEL Carrier frequency selection for FTM0 output channel 8 1 read-write 0 FTM1 channel 1 output provides the carrier signal for FTM0 Timer Modulation mode. #0 1 LPTMR0 prescaler output provides the carrier signal for FTM0 Timer Modulation mode. #1 FTM0OCH0SRC FTM0 channel 0 output source 16 1 read-write 0 FTM0_CH0 pin is output of FTM0 channel 0 output #0 1 FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH1SRC FTM0 channel 1 output source 17 1 read-write 0 FTM0_CH1 pin is output of FTM0 channel 1 output #0 1 FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH2SRC FTM0 channel 2 output source 18 1 read-write 0 FTM0_CH2 pin is output of FTM0 channel 2 output #0 1 FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH3SRC FTM0 channel 3 output source 19 1 read-write 0 FTM0_CH3 pin is output of FTM0 channel 3 output #0 1 FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH4SRC FTM0 channel 4 output source 20 1 read-write 0 FTM0_CH4 pin is output of FTM0 channel 4 output #0 1 FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH5SRC FTM0 channel 5 output source 21 1 read-write 0 FTM0_CH5 pin is output of FTM0 channel 5 output #0 1 FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH6SRC FTM0 channel 6 output source 22 1 read-write 0 FTM0_CH6 pin is output of FTM0 channel 6 output #0 1 FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0OCH7SRC FTM0 channel 7 output source 23 1 read-write 0 FTM0_CH7 pin is output of FTM0 channel 7 output #0 1 FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by carrier frequency clock, as per FTM0CFSEL #1 FTM0SYNCBIT FTM0 Hardware Trigger 0 Software Synchronization 0 1 read-write 0 No effect #0 1 Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert. #1 FTM1SYNCBIT FTM1 Hardware Trigger 0 Software Synchronization 1 1 read-write 0 No effect. #0 1 Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert. #1 FTM2SYNCBIT FTM2 Hardware Trigger 0 Software Synchronization 2 1 read-write 0 No effect. #0 1 Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert. #1 FTM3CFSEL Carrier frequency selection for FTM3 output channel 9 1 read-write 0 FTM1 channel 1 output provides the carrier signal for FTM3 Timer Modulation mode. #0 1 LPTMR0 prescaler output provides the carrier signal for FTM3 Timer Modulation mode. #1 FTM3OCH0SRC FTM3 channel 0 output source 24 1 read-write 0 FTM3_CH0 pin is output of FTM3 channel 0 output #0 1 FTM3_CH0 pin is output of FTM3 channel 0 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH1SRC FTM3 channel 1 output source 25 1 read-write 0 FTM3_CH1 pin is output of FTM3 channel 1 output #0 1 FTM3_CH1 pin is output of FTM3 channel 1 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH2SRC FTM3 channel 2 output source 26 1 read-write 0 FTM3_CH2 pin is output of FTM3 channel 2 output #0 1 FTM3_CH2 pin is output of FTM3 channel 2 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH3SRC FTM3 channel 3 output source 27 1 read-write 0 FTM3_CH3 pin is output of FTM3 channel 3 output #0 1 FTM3_CH3 pin is output of FTM3 channel 3 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH4SRC FTM3 channel 4 output source 28 1 read-write 0 FTM3_CH4 pin is output of FTM3 channel 4 output #0 1 FTM3_CH4 pin is output of FTM3 channel 4 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH5SRC FTM3 channel 5 output source 29 1 read-write 0 FTM3_CH5 pin is output of FTM3 channel 5 output #0 1 FTM3_CH5 pin is output of FTM3 channel 5 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH6SRC FTM3 channel 6 output source 30 1 read-write 0 FTM3_CH6 pin is output of FTM3 channel 6 output #0 1 FTM3_CH6 pin is output of FTM3 channel 6 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3OCH7SRC FTM3 channel 7 output source 31 1 read-write 0 FTM3_CH7 pin is output of FTM3 channel 7 output #0 1 FTM3_CH7 pin is output of FTM3 channel 7 output modulated by carrier frequency clock, as per FTM3CFSEL. #1 FTM3SYNCBIT FTM3 Hardware Trigger 0 Software Synchronization 3 1 read-write 0 No effect. #0 1 Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert. #1 SOPT9 System Options Register 9 0x1020 32 read-write n 0x0 0x0 FTM0CLKSEL FlexTimer 0 External Clock Pin Select 24 2 read-write 00 FTM0 external clock driven by FTM_CLK0 pin #00 01 FTM0 external clock driven by FTM_CLK1 pin #01 10 FTM0 external clock driven by FTM_CLK2 pin #10 FTM1CLKSEL FlexTimer 1 External Clock Pin Select 26 2 read-write 00 FTM1 external clock driven by FTM_CLK0 pin #00 01 FTM1 external clock driven by FTM_CLK1 pin #01 10 FTM1 external clock driven by FTM_CLK2 pin #10 FTM1ICH0SRC FTM1 channel 0 input capture source select 4 2 read-write 00 FTM1_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 FTM1ICH1SRC FTM1 channel 0 input capture source select 6 1 read-write 0 FTM1_CH1 signal #0 1 Exclusive OR of FTM1_CH1, FTM1_CH0, and XBARA output 42 (XBARA output 42 can also trigger HSADC1A sync0) #1 FTM2CLKSEL FlexTimer 2 External Clock Pin Select 28 2 read-write 00 FTM2 external clock driven by FTM_CLK0 pin #00 01 FTM2 external clock driven by FTM_CLK1 pin #01 10 FTM2 external clock driven by FTM_CLK2 pin #10 FTM2ICH0SRC FTM2 channel 0 input capture source select 8 2 read-write 00 FTM2_CH0 signal #00 01 CMP0 output #01 10 CMP1 output #10 FTM2ICH1SRC FTM2 channel 1 input capture source select 10 1 read-write 0 FTM2_CH1 signal #0 1 Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1 #1 FTM3CLKSEL FlexTimer 3 External Clock Pin Select 30 2 read-write 00 FTM3 external clock driven by FTM_CLK0 pin #00 01 FTM3 external clock driven by FTM_CLK1 pin #01 10 FTM3 external clock driven by FTM_CLK2 pin #10 UIDH Unique Identification Register High 0x1054 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only UIDL Unique Identification Register Low 0x1060 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only UIDMH Unique Identification Register Mid-High 0x1058 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only UIDML Unique Identification Register Mid Low 0x105C 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only WDOGC WDOG Control Register 0x1100 32 read-write n 0x0 0x0 WDOGCLKS WDOG Clock Select 1 1 read-write 0 1 kHz LPO clock is source to WDOG #0 1 MCGIRCLK is source to WDOG #1 SMC System Mode Controller SMC 0x0 0x0 0x4 registers n PMCTRL Power Mode Control register 0x1 8 read-write n 0x0 0x0 RUNM Run Mode Control 5 2 read-write 00 Normal Run mode (RUN) #00 10 Very-Low-Power Run mode (VLPR) #10 11 High Speed Run mode (HSRUN) #11 STOPA Stop Aborted 3 1 read-only 0 The previous stop mode entry was successsful. #0 1 The previous stop mode entry was aborted. #1 STOPM Stop Mode Control 0 3 read-write 000 Normal Stop (STOP) #000 010 Very-Low-Power Stop (VLPS) #010 100 Very-Low-Leakage Stop (VLLSx) #100 110 Reseved #110 PMPROT Power Mode Protection register 0x0 8 read-write n 0x0 0x0 AHSRUN Allow High Speed Run mode 7 1 read-write 0 HSRUN is not allowed #0 1 HSRUN is allowed #1 AVLLS Allow Very-Low-Leakage Stop Mode 1 1 read-write 0 Any VLLSx mode is not allowed #0 1 Any VLLSx mode is allowed #1 AVLP Allow Very-Low-Power Modes 5 1 read-write 0 VLPR, VLPW, and VLPS are not allowed. #0 1 VLPR, VLPW, and VLPS are allowed. #1 PMSTAT Power Mode Status register 0x3 8 read-only n 0x0 0x0 PMSTAT Power Mode Status 0 8 read-only STOPCTRL Stop Control Register 0x2 8 read-write n 0x0 0x0 LPOPO LPO Power Option 3 1 read-write 0 LPO clock is enabled in VLLSx #0 1 LPO clock is disabled in VLLSx #1 PORPO POR Power Option 5 1 read-write 0 POR detect circuit is enabled in VLLS0 #0 1 POR detect circuit is disabled in VLLS0 #1 PSTOPO Partial Stop Option 6 2 read-write 00 STOP - Normal Stop mode #00 01 PSTOP1 - Partial Stop with both system and bus clocks disabled #01 10 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled #10 RAM2PO RAM2 Power Option 4 1 read-write 0 RAM2 not powered in VLLS2 #0 1 RAM2 powered in VLLS2 #1 VLLSM VLLS Mode Control 0 3 read-write 000 VLLS0 #000 001 VLLS1 #001 010 VLLS2 #010 011 VLLS3 #011 SPI0 Serial Peripheral Interface SPI 0x0 0x0 0x8C registers n SPI0 26 CTAR0 Clock and Transfer Attributes Register (In Master Mode) SPI0 0x18 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR1 Clock and Transfer Attributes Register (In Master Mode) SPI0 0x28 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI0 0xC 32 read-write n 0x0 0x0 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write MCR Module Configuration Register 0x0 32 read-write n 0x0 0x0 CLR_RXF CLR_RXF 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 PCSIS Peripheral Chip Select x Inactive State 16 6 read-write 0 The inactive state of PCSx is low. #0 1 The inactive state of PCSx is high. #1 PCSSE Peripheral Chip Select Strobe Enable 25 1 read-write 0 PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. #0 1 PCS5/ PCSS is used as an active-low PCS Strobe signal. #1 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 POPR POP RX FIFO Register 0x38 32 read-only n 0x0 0x0 RXDATA Received Data 0 32 read-only PUSHR PUSH TX FIFO Register In Master Mode SPI0 0x34 32 read-write n 0x0 0x0 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 PCS Select which PCS signals are to be asserted for the transfer 16 6 read-write 0 Negate the PCS[x] signal. #0 1 Assert the PCS[x] signal. #1 TXDATA Transmit Data 0 16 read-write PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI0 0x34 32 read-write n 0x0 0x0 TXDATA Transmit Data 0 16 read-write RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write n 0x0 0x0 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 RXFR0 Receive FIFO Registers 0xF8 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR1 Receive FIFO Registers 0x178 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR2 Receive FIFO Registers 0x1FC 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR3 Receive FIFO Registers 0x284 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only SR Status Register 0x2C 32 read-write n 0x0 0x0 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 POPNXTPTR Pop Next Pointer 0 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 RXCTR RX FIFO Counter 4 4 read-only TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 TXCTR TX FIFO Counter 12 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCR Transfer Count Register 0x8 32 read-write n 0x0 0x0 SPI_TCNT SPI Transfer Counter 16 16 read-write TXFR0 Transmit FIFO Registers 0x78 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR1 Transmit FIFO Registers 0xB8 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR2 Transmit FIFO Registers 0xFC 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR3 Transmit FIFO Registers 0x144 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only SPI1 Serial Peripheral Interface SPI 0x0 0x0 0x8C registers n SPI1 27 CTAR0 Clock and Transfer Attributes Register (In Master Mode) SPI1 0x18 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR1 Clock and Transfer Attributes Register (In Master Mode) SPI1 0x28 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI1 0xC 32 read-write n 0x0 0x0 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write MCR Module Configuration Register 0x0 32 read-write n 0x0 0x0 CLR_RXF CLR_RXF 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 PCSIS Peripheral Chip Select x Inactive State 16 6 read-write 0 The inactive state of PCSx is low. #0 1 The inactive state of PCSx is high. #1 PCSSE Peripheral Chip Select Strobe Enable 25 1 read-write 0 PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. #0 1 PCS5/ PCSS is used as an active-low PCS Strobe signal. #1 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 POPR POP RX FIFO Register 0x38 32 read-only n 0x0 0x0 RXDATA Received Data 0 32 read-only PUSHR PUSH TX FIFO Register In Master Mode SPI1 0x34 32 read-write n 0x0 0x0 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 PCS Select which PCS signals are to be asserted for the transfer 16 6 read-write 0 Negate the PCS[x] signal. #0 1 Assert the PCS[x] signal. #1 TXDATA Transmit Data 0 16 read-write PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI1 0x34 32 read-write n 0x0 0x0 TXDATA Transmit Data 0 16 read-write RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write n 0x0 0x0 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 RXFR0 Receive FIFO Registers 0xF8 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR1 Receive FIFO Registers 0x178 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR2 Receive FIFO Registers 0x1FC 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR3 Receive FIFO Registers 0x284 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only SR Status Register 0x2C 32 read-write n 0x0 0x0 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 POPNXTPTR Pop Next Pointer 0 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 RXCTR RX FIFO Counter 4 4 read-only TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 TXCTR TX FIFO Counter 12 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCR Transfer Count Register 0x8 32 read-write n 0x0 0x0 SPI_TCNT SPI Transfer Counter 16 16 read-write TXFR0 Transmit FIFO Registers 0x78 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR1 Transmit FIFO Registers 0xB8 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR2 Transmit FIFO Registers 0xFC 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR3 Transmit FIFO Registers 0x144 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only SPI2 Serial Peripheral Interface SPI 0x0 0x0 0x8C registers n SPI2 65 CTAR0 Clock and Transfer Attributes Register (In Master Mode) SPI2 0x18 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR1 Clock and Transfer Attributes Register (In Master Mode) SPI2 0x28 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR_SLAVE Clock and Transfer Attributes Register (In Slave Mode) SPI2 0xC 32 read-write n 0x0 0x0 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 4 read-write MCR Module Configuration Register 0x0 32 read-write n 0x0 0x0 CLR_RXF CLR_RXF 10 1 write-only 0 Do not clear the RX FIFO counter. #0 1 Clear the RX FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the TX FIFO counter. #0 1 Clear the TX FIFO counter. #1 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 DCONF SPI Configuration. 28 2 read-only 00 SPI #00 DIS_RXF Disable Receive FIFO 12 1 read-write 0 RX FIFO is enabled. #0 1 RX FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 TX FIFO is enabled. #0 1 TX FIFO is disabled. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on the module. #0 1 Doze mode disables the module. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in Debug mode. #0 1 Halt serial transfers in Debug mode. #1 HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 MDIS Module Disable 14 1 read-write 0 Enables the module clocks. #0 1 Allows external logic to disable the module clocks. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 Enables Slave mode #0 1 Enables Master mode #1 MTFE Modified Transfer Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 PCSIS Peripheral Chip Select x Inactive State 16 6 read-write 0 The inactive state of PCSx is low. #0 1 The inactive state of PCSx is high. #1 PCSSE Peripheral Chip Select Strobe Enable 25 1 read-write 0 PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. #0 1 PCS5/ PCSS is used as an active-low PCS Strobe signal. #1 ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 SMPL_PT Sample Point 8 2 read-write 00 0 protocol clock cycles between SCK edge and SIN sample #00 01 1 protocol clock cycle between SCK edge and SIN sample #01 10 2 protocol clock cycles between SCK edge and SIN sample #10 POPR POP RX FIFO Register 0x38 32 read-only n 0x0 0x0 RXDATA Received Data 0 32 read-only PUSHR PUSH TX FIFO Register In Master Mode SPI2 0x34 32 read-write n 0x0 0x0 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 CTAS Clock and Transfer Attributes Select 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 CTCNT Clear Transfer Counter 26 1 read-write 0 Do not clear the TCR[TCNT] field. #0 1 Clear the TCR[TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 PCS Select which PCS signals are to be asserted for the transfer 16 6 read-write 0 Negate the PCS[x] signal. #0 1 Assert the PCS[x] signal. #1 TXDATA Transmit Data 0 16 read-write PUSHR_SLAVE PUSH TX FIFO Register In Slave Mode SPI2 0x34 32 read-write n 0x0 0x0 TXDATA Transmit Data 0 16 read-write RSER DMA/Interrupt Request Select and Enable Register 0x30 32 read-write n 0x0 0x0 EOQF_RE Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled. #0 1 RFDF interrupt or DMA requests are enabled. #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 RXFR0 Receive FIFO Registers 0xF8 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR1 Receive FIFO Registers 0x178 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR2 Receive FIFO Registers 0x1FC 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR3 Receive FIFO Registers 0x284 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only SR Status Register 0x2C 32 read-write n 0x0 0x0 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 POPNXTPTR Pop Next Pointer 0 4 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 RX FIFO is empty. #0 1 RX FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 RXCTR RX FIFO Counter 4 4 read-only TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 TX FIFO is full. #0 1 TX FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No TX FIFO underflow. #0 1 TX FIFO underflow has occurred. #1 TXCTR TX FIFO Counter 12 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (The module is in Stopped state). #0 1 Transmit and receive operations are enabled (The module is in Running state). #1 TCR Transfer Count Register 0x8 32 read-write n 0x0 0x0 SPI_TCNT SPI Transfer Counter 16 16 read-write TXFR0 Transmit FIFO Registers 0x78 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR1 Transmit FIFO Registers 0xB8 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR2 Transmit FIFO Registers 0xFC 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR3 Transmit FIFO Registers 0x144 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TRNG0 RNG TRNG0 0x0 0x0 0xF8 registers n TRNG0 23 ENT0 RNG TRNG Entropy Read Register 0x40 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT1 RNG TRNG Entropy Read Register 0x44 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT10 RNG TRNG Entropy Read Register 0x68 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT11 RNG TRNG Entropy Read Register 0x6C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT12 RNG TRNG Entropy Read Register 0x70 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT13 RNG TRNG Entropy Read Register 0x74 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT14 RNG TRNG Entropy Read Register 0x78 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT15 RNG TRNG Entropy Read Register 0x7C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT2 RNG TRNG Entropy Read Register 0x48 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT3 RNG TRNG Entropy Read Register 0x4C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT4 RNG TRNG Entropy Read Register 0x50 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT5 RNG TRNG Entropy Read Register 0x54 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT6 RNG TRNG Entropy Read Register 0x58 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT7 RNG TRNG Entropy Read Register 0x5C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT8 RNG TRNG Entropy Read Register 0x60 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT9 RNG TRNG Entropy Read Register 0x64 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only FRQCNT RNG Frequency Count Register TRNG0 0x1C 32 read-only n 0x0 0x0 FRQ_CT Frequency Count 0 22 read-only FRQMAX RNG Frequency Count Maximum Limit Register TRNG0 0x1C 32 read-write n 0x0 0x0 FRQ_MAX Frequency Counter Maximum Limit 0 22 read-write FRQMIN RNG Frequency Count Minimum Limit Register 0x18 32 read-write n 0x0 0x0 FRQ_MIN Frequency Count Minimum Limit 0 22 read-write INT_CTRL RNG Interrupt Control Register 0xB4 32 read-write n 0x0 0x0 ENT_VAL Same behavior as bit 0 above. 1 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 FRQ_CT_FAIL Same behavior as bit 0 above. 2 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write 0 Corresponding bit of INT_STATUS cleared. #0 1 Corresponding bit of INT_STATUS active. #1 UNUSED Reserved but writeable. 3 29 read-write INT_MASK RNG Mask Register 0xB8 32 read-write n 0x0 0x0 ENT_VAL Same behavior as bit 0 above. 1 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 FRQ_CT_FAIL Same behavior as bit 0 above. 2 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write 0 Corresponding interrupt of INT_STATUS is masked. #0 1 Corresponding bit of INT_STATUS is active. #1 INT_STATUS RNG Interrupt Status Register 0xBC 32 read-write n 0x0 0x0 ENT_VAL Read only: Entropy Valid 1 1 read-only 0 Busy generation entropy. Any value read is invalid. #0 1 TRNG can be stopped and entropy is valid if read. #1 FRQ_CT_FAIL Read only: Frequency Count Fail 2 1 read-write 0 No hardware nor self test frequency errors. #0 1 The frequency counter has detected a failure. #1 HW_ERR Read: Error status 0 1 read-only 0 no error #0 1 error detected. #1 MCTL RNG Miscellaneous Control Register 0x0 32 read-write n 0x0 0x0 ENT_VAL Read only: Entropy Valid 10 1 read-only ERR Read: Error status 12 1 read-write FCT_FAIL Read only: Frequency Count Fail 8 1 read-only FCT_VAL Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT. 9 1 read-only FOR_SCLK Force System Clock 7 1 read-write OSC_DIV Oscillator Divide 2 2 read-write 00 use ring oscillator with no divide #00 01 use ring oscillator divided-by-2 #01 10 use ring oscillator divided-by-4 #10 11 use ring oscillator divided-by-8 #11 PRGM Programming Mode Select 16 1 read-write RST_DEF Reset Defaults 6 1 write-only SAMP_MODE Sample Mode 0 2 read-write 00 use Von Neumann data into both Entropy shifter and Statistical Checker #00 01 use raw data into both Entropy shifter and Statistical Checker #01 10 use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker #10 TRNG_ACC TRNG Access Mode 5 1 read-write TSTOP_OK TRNG_OK_TO_STOP 13 1 read-only TST_OUT Read only: Test point inside ring oscillator. 11 1 read-only UNUSED This bit is unused but write-able. Must be left as zero. 4 1 read-write PKRCNT10 RNG Statistical Check Poker Count 1 and 0 Register 0x80 32 read-only n 0x0 0x0 PKR_0_CT Poker 0h Count 0 16 read-only PKR_1_CT Poker 1h Count 16 16 read-only PKRCNT32 RNG Statistical Check Poker Count 3 and 2 Register 0x84 32 read-only n 0x0 0x0 PKR_2_CT Poker 2h Count 0 16 read-only PKR_3_CT Poker 3h Count 16 16 read-only PKRCNT54 RNG Statistical Check Poker Count 5 and 4 Register 0x88 32 read-only n 0x0 0x0 PKR_4_CT Poker 4h Count 0 16 read-only PKR_5_CT Poker 5h Count 16 16 read-only PKRCNT76 RNG Statistical Check Poker Count 7 and 6 Register 0x8C 32 read-only n 0x0 0x0 PKR_6_CT Poker 6h Count 0 16 read-only PKR_7_CT Poker 7h Count 16 16 read-only PKRCNT98 RNG Statistical Check Poker Count 9 and 8 Register 0x90 32 read-only n 0x0 0x0 PKR_8_CT Poker 8h Count 0 16 read-only PKR_9_CT Poker 9h Count 16 16 read-only PKRCNTBA RNG Statistical Check Poker Count B and A Register 0x94 32 read-only n 0x0 0x0 PKR_A_CT Poker Ah Count 0 16 read-only PKR_B_CT Poker Bh Count 16 16 read-only PKRCNTDC RNG Statistical Check Poker Count D and C Register 0x98 32 read-only n 0x0 0x0 PKR_C_CT Poker Ch Count 0 16 read-only PKR_D_CT Poker Dh Count 16 16 read-only PKRCNTFE RNG Statistical Check Poker Count F and E Register 0x9C 32 read-only n 0x0 0x0 PKR_E_CT Poker Eh Count 0 16 read-only PKR_F_CT Poker Fh Count 16 16 read-only PKRMAX RNG Poker Maximum Limit Register TRNG0 0xC 32 read-write n 0x0 0x0 PKR_MAX Poker Maximum Limit 0 24 read-write PKRRNG RNG Poker Range Register 0x8 32 read-write n 0x0 0x0 PKR_RNG Poker Range 0 16 read-write PKRSQ RNG Poker Square Calculation Result Register TRNG0 0xC 32 read-only n 0x0 0x0 PKR_SQ Poker Square Calculation Result 0 24 read-only SBLIM RNG Sparse Bit Limit Register TRNG0 0x14 32 read-write n 0x0 0x0 SB_LIM Sparse Bit Limit 0 10 read-write SCMC RNG Statistical Check Monobit Count Register TRNG0 0x20 32 read-only n 0x0 0x0 MONO_CT Monobit Count 0 16 read-only SCMISC RNG Statistical Check Miscellaneous Register 0x4 32 read-write n 0x0 0x0 LRUN_MAX LONG RUN MAX LIMIT 0 8 read-write RTY_CT RETRY COUNT 16 4 read-write SCML RNG Statistical Check Monobit Limit Register TRNG0 0x20 32 read-write n 0x0 0x0 MONO_MAX Monobit Maximum Limit 0 16 read-write MONO_RNG Monobit Range 16 16 read-write SCR1C RNG Statistical Check Run Length 1 Count Register TRNG0 0x24 32 read-only n 0x0 0x0 R1_0_CT Runs of Zero, Length 1 Count 0 15 read-only R1_1_CT Runs of One, Length 1 Count 16 15 read-only SCR1L RNG Statistical Check Run Length 1 Limit Register TRNG0 0x24 32 read-write n 0x0 0x0 RUN1_MAX Run Length 1 Maximum Limit 0 15 read-write RUN1_RNG Run Length 1 Range 16 15 read-write SCR2C RNG Statistical Check Run Length 2 Count Register TRNG0 0x28 32 read-only n 0x0 0x0 R2_0_CT Runs of Zero, Length 2 Count 0 14 read-only R2_1_CT Runs of One, Length 2 Count 16 14 read-only SCR2L RNG Statistical Check Run Length 2 Limit Register TRNG0 0x28 32 read-write n 0x0 0x0 RUN2_MAX Run Length 2 Maximum Limit 0 14 read-write RUN2_RNG Run Length 2 Range 16 14 read-write SCR3C RNG Statistical Check Run Length 3 Count Register TRNG0 0x2C 32 read-only n 0x0 0x0 R3_0_CT Runs of Zeroes, Length 3 Count 0 13 read-only R3_1_CT Runs of Ones, Length 3 Count 16 13 read-only SCR3L RNG Statistical Check Run Length 3 Limit Register TRNG0 0x2C 32 read-write n 0x0 0x0 RUN3_MAX Run Length 3 Maximum Limit 0 13 read-write RUN3_RNG Run Length 3 Range 16 13 read-write SCR4C RNG Statistical Check Run Length 4 Count Register TRNG0 0x30 32 read-only n 0x0 0x0 R4_0_CT Runs of Zero, Length 4 Count 0 12 read-only R4_1_CT Runs of One, Length 4 Count 16 12 read-only SCR4L RNG Statistical Check Run Length 4 Limit Register TRNG0 0x30 32 read-write n 0x0 0x0 RUN4_MAX Run Length 4 Maximum Limit 0 12 read-write RUN4_RNG Run Length 4 Range 16 12 read-write SCR5C RNG Statistical Check Run Length 5 Count Register TRNG0 0x34 32 read-only n 0x0 0x0 R5_0_CT Runs of Zero, Length 5 Count 0 11 read-only R5_1_CT Runs of One, Length 5 Count 16 11 read-only SCR5L RNG Statistical Check Run Length 5 Limit Register TRNG0 0x34 32 read-write n 0x0 0x0 RUN5_MAX Run Length 5 Maximum Limit 0 11 read-write RUN5_RNG Run Length 5 Range 16 11 read-write SCR6PC RNG Statistical Check Run Length 6+ Count Register TRNG0 0x38 32 read-only n 0x0 0x0 R6P_0_CT Runs of Zero, Length 6+ Count 0 11 read-only R6P_1_CT Runs of One, Length 6+ Count 16 11 read-only SCR6PL RNG Statistical Check Run Length 6+ Limit Register TRNG0 0x38 32 read-write n 0x0 0x0 RUN6P_MAX Run Length 6+ Maximum Limit 0 11 read-write RUN6P_RNG Run Length 6+ Range 16 11 read-write SDCTL RNG Seed Control Register 0x10 32 read-write n 0x0 0x0 ENT_DLY Entropy Delay 16 16 read-write SAMP_SIZE Sample Size 0 16 read-write SEC_CFG RNG Security Configuration Register 0xB0 32 read-write n 0x0 0x0 NO_PRGM If set the TRNG registers cannot be programmed 1 1 read-write 0 Programability of registers controlled only by the RNG Miscellaneous Control Register's access mode bit. #0 1 Overides RNG Miscellaneous Control Register access mode and prevents TRNG register programming. #1 SH0 Reserved. DRNG specific, not applicable to this version. 0 1 read-write 0 See DRNG version. #0 1 See DRNG version. #1 SK_VAL Reserved. DRNG-specific, not applicable to this version. 2 1 read-write 0 See DRNG version. #0 1 See DRNG version. #1 STATUS RNG Status Register 0x3C 32 read-only n 0x0 0x0 RETRY_CT RETRY COUNT 16 4 read-only TF1BR0 Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed. 0 1 read-only TF1BR1 Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed. 1 1 read-only TF2BR0 Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed. 2 1 read-only TF2BR1 Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed. 3 1 read-only TF3BR0 Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed. 4 1 read-only TF3BR1 Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed. 5 1 read-only TF4BR0 Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed. 6 1 read-only TF4BR1 Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed. 7 1 read-only TF5BR0 Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed. 8 1 read-only TF5BR1 Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed. 9 1 read-only TF6PBR0 Test Fail, 6 Plus Bit Run, Sampling 0s 10 1 read-only TF6PBR1 Test Fail, 6 Plus Bit Run, Sampling 1s 11 1 read-only TFLR Test Fail, Long Run. If TFLR=1, the Long Run Test has failed. 13 1 read-only TFMB Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed. 15 1 read-only TFP Test Fail, Poker. If TFP=1, the Poker Test has failed. 14 1 read-only TFSB Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed. 12 1 read-only TOTSAM RNG Total Samples Register TRNG0 0x14 32 read-only n 0x0 0x0 TOT_SAM Total Samples 0 20 read-only VID1 RNG Version ID Register (MS) 0xF0 32 read-only n 0x0 0x0 RNG_IP_ID Shows the Freescale IP ID. 16 16 read-only RNG_MAJ_REV Shows the Freescale IP's Major revision of the TRNG. 8 8 read-only 0x01 Major revision number for TRNG. #1 RNG_MIN_REV Shows the Freescale IP's Minor revision of the TRNG. 0 8 read-only 0x00 Minor revision number for TRNG. #0 VID2 RNG Version ID Register (LS) 0xF4 32 read-only n 0x0 0x0 RNG_CONFIG_OPT Shows the Freescale IP's Configuaration options for the TRNG. 0 8 read-only 0x00 TRNG_CONFIG_OPT for TRNG. #0 RNG_ECO_REV Shows the Freescale IP's ECO revision of the TRNG. 8 8 read-only 0x00 TRNG_ECO_REV for TRNG. #0 RNG_ERA Shows the Freescale compile options for the TRNG. 24 8 read-only 0x00 COMPILE_OPT for TRNG. #0 RNG_INTG_OPT Shows the Freescale integration options for the TRNG. 16 8 read-only 0x00 INTG_OPT for TRNG. #0 UART0 Serial Communication Interface UART 0x0 0x0 0x40 registers n UART0_RX_TX 31 UART0_ERR 32 AP7816A_T0 UART 7816 ATR Duration Timer Register A 0x3A 8 read-write n 0x0 0x0 ADTI_H ATR Duration Time Integer High (C7816[TTYPE] = 0) 0 8 read-write AP7816B_T0 UART 7816 ATR Duration Timer Register B 0x3B 8 read-write n 0x0 0x0 ADTI_L ATR Duration Time Integer Low (C7816[TTYPE] = 0) 0 8 read-write BDH UART Baud Rate Registers: High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt or DMA Request Enable 7 1 read-write 0 LBKDIF interrupt and DMA transfer requests disabled. #0 1 LBKDIF interrupt or DMA transfer requests enabled. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 SBNS Stop Bit Number Select 5 1 read-write 0 Data frame consists of a single stop bit. #0 1 Data frame consists of two stop bits. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 LBKDDMAS LIN Break Detect DMA Select Bit 3 1 read-write 0 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service. #0 1 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer. #1 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 C7816 UART 7816 Control Register 0x18 8 read-write n 0x0 0x0 ANACK Generate NACK on Error 3 1 read-write 0 No NACK is automatically generated. #0 1 A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected. #1 INIT Detect Initial Character 2 1 read-write 0 Normal operating mode. Receiver does not seek to identify initial character. #0 1 Receiver searches for initial character. #1 ISO_7816E ISO-7816 Functionality Enabled 0 1 read-write 0 ISO-7816 functionality is turned off/not enabled. #0 1 ISO-7816 functionality is turned on/enabled. #1 ONACK Generate NACK on Overflow 4 1 read-write 0 The received data does not generate a NACK when the receipt of the data results in an overflow event. #0 1 If the receiver buffer overflows, a NACK is automatically sent on a received character. #1 TTYPE Transfer Type 1 1 read-write 0 T = 0 per the ISO-7816 specification. #0 1 T = 1 per the ISO-7816 specification. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY The current received dataword contained in D and C3[R8] was received with noise. 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE The current received dataword contained in D and C3[R8] was received with a parity error. 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 ET7816 UART 7816 Error Threshold Register 0x1E 8 read-write n 0x0 0x0 RXTHRESHOLD Receive NACK Threshold 0 4 read-write TXTHRESHOLD Transmit NACK Threshold 4 4 read-write 0 TXT asserts on the first NACK that is received. #0000 1 TXT asserts on the second NACK that is received. #0001 IE7816 UART 7816 Interrupt Enable Register 0x19 8 read-write n 0x0 0x0 ADTE ATR Duration Timer Interrupt Enable 3 1 read-write 0 The assertion of IS7816[ADT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[ADT] results in the generation of an interrupt. #1 BWTE Block Wait Timer Interrupt Enable 5 1 read-write 0 The assertion of IS7816[BWT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[BWT] results in the generation of an interrupt. #1 CWTE Character Wait Timer Interrupt Enable 6 1 read-write 0 The assertion of IS7816[CWT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[CWT] results in the generation of an interrupt. #1 GTVE Guard Timer Violated Interrupt Enable 2 1 read-write 0 The assertion of IS7816[GTV] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[GTV] results in the generation of an interrupt. #1 INITDE Initial Character Detected Interrupt Enable 4 1 read-write 0 The assertion of IS7816[INITD] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[INITD] results in the generation of an interrupt. #1 RXTE Receive Threshold Exceeded Interrupt Enable 0 1 read-write 0 The assertion of IS7816[RXT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[RXT] results in the generation of an interrupt. #1 TXTE Transmit Threshold Exceeded Interrupt Enable 1 1 read-write 0 The assertion of IS7816[TXT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[TXT] results in the generation of an interrupt. #1 WTE Wait Timer Interrupt Enable 7 1 read-write 0 The assertion of IS7816[WT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[WT] results in the generation of an interrupt. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 IS7816 UART 7816 Interrupt Status Register 0x1A 8 read-write n 0x0 0x0 ADT ATR Duration Time Interrupt 3 1 read-write 0 ATR Duration time (ADT) has not been violated. #0 1 ATR Duration time (ADT) has been violated. #1 BWT Block Wait Timer Interrupt 5 1 read-write 0 Block wait time (BWT) has not been violated. #0 1 Block wait time (BWT) has been violated. #1 CWT Character Wait Timer Interrupt 6 1 read-write 0 Character wait time (CWT) has not been violated. #0 1 Character wait time (CWT) has been violated. #1 GTV Guard Timer Violated Interrupt 2 1 read-write 0 A guard time (GT, CGT, or BGT) has not been violated. #0 1 A guard time (GT, CGT, or BGT) has been violated. #1 INITD Initial Character Detected Interrupt 4 1 read-write 0 A valid initial character has not been received. #0 1 A valid initial character has been received. #1 RXT Receive Threshold Exceeded Interrupt 0 1 read-write 0 The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD]. #0 1 The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD]. #1 TXT Transmit Threshold Exceeded Interrupt 1 1 read-write 0 The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD]. #0 1 The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD]. #1 WT Wait Timer Interrupt 7 1 read-write 0 Wait time (WT) has not been violated. #0 1 Wait time (WT) has been violated. #1 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. See Hardware flow control #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) Ensure that C2[TE] is asserted before assertion of this bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character detection is disabled. #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TL7816 UART 7816 Transmit Length Register 0x1F 8 read-write n 0x0 0x0 TLEN Transmit Length 0 8 read-write TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write WF7816 UART 7816 Wait FD Register 0x1D 8 read-write n 0x0 0x0 GTFD FD Multiplier 0 8 read-write WGP7816_T1 UART 7816 Wait and Guard Parameter Register 0x3E 8 read-write n 0x0 0x0 BGI Block Guard Time Integer (C7816[TTYPE] = 1) 0 4 read-write CWI1 Character Wait Time Integer 1 (C7816[TTYPE] = 1) 4 4 read-write WN7816 UART 7816 Wait N Register 0x1C 8 read-write n 0x0 0x0 GTN Guard Band N 0 8 read-write WP7816 UART 7816 Wait Parameter Register 0x1B 8 read-write n 0x0 0x0 WTX Wait Time Multiplier (C7816[TTYPE] = 1) 0 8 read-write WP7816A_T0 UART 7816 Wait Parameter Register A UART0 0x3C 8 read-write n 0x0 0x0 WI_H Wait Time Integer High (C7816[TTYPE] = 0) 0 8 read-write WP7816A_T1 UART 7816 Wait Parameter Register A UART0 0x3C 8 read-write n 0x0 0x0 BWI_H Block Wait Time Integer High (C7816[TTYPE] = 1) 0 8 read-write WP7816B_T0 UART 7816 Wait Parameter Register B UART0 0x3D 8 read-write n 0x0 0x0 WI_L Wait Time Integer Low (C7816[TTYPE] = 0) 0 8 read-write WP7816B_T1 UART 7816 Wait Parameter Register B UART0 0x3D 8 read-write n 0x0 0x0 BWI_L Block Wait Time Integer Low (C7816[TTYPE] = 1) 0 8 read-write WP7816C_T1 UART 7816 Wait Parameter Register C 0x3F 8 read-write n 0x0 0x0 CWI2 Character Wait Time Integer 2 (C7816[TTYPE] = 1) 0 5 read-write UART1 Serial Communication Interface UART 0x0 0x0 0x40 registers n UART1_RX_TX 33 UART1_ERR 34 AP7816A_T0 UART 7816 ATR Duration Timer Register A 0x3A 8 read-write n 0x0 0x0 ADTI_H ATR Duration Time Integer High (C7816[TTYPE] = 0) 0 8 read-write AP7816B_T0 UART 7816 ATR Duration Timer Register B 0x3B 8 read-write n 0x0 0x0 ADTI_L ATR Duration Time Integer Low (C7816[TTYPE] = 0) 0 8 read-write BDH UART Baud Rate Registers: High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt or DMA Request Enable 7 1 read-write 0 LBKDIF interrupt and DMA transfer requests disabled. #0 1 LBKDIF interrupt or DMA transfer requests enabled. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 SBNS Stop Bit Number Select 5 1 read-write 0 Data frame consists of a single stop bit. #0 1 Data frame consists of two stop bits. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 LBKDDMAS LIN Break Detect DMA Select Bit 3 1 read-write 0 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service. #0 1 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer. #1 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 C7816 UART 7816 Control Register 0x18 8 read-write n 0x0 0x0 ANACK Generate NACK on Error 3 1 read-write 0 No NACK is automatically generated. #0 1 A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected. #1 INIT Detect Initial Character 2 1 read-write 0 Normal operating mode. Receiver does not seek to identify initial character. #0 1 Receiver searches for initial character. #1 ISO_7816E ISO-7816 Functionality Enabled 0 1 read-write 0 ISO-7816 functionality is turned off/not enabled. #0 1 ISO-7816 functionality is turned on/enabled. #1 ONACK Generate NACK on Overflow 4 1 read-write 0 The received data does not generate a NACK when the receipt of the data results in an overflow event. #0 1 If the receiver buffer overflows, a NACK is automatically sent on a received character. #1 TTYPE Transfer Type 1 1 read-write 0 T = 0 per the ISO-7816 specification. #0 1 T = 1 per the ISO-7816 specification. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY The current received dataword contained in D and C3[R8] was received with noise. 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE The current received dataword contained in D and C3[R8] was received with a parity error. 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 ET7816 UART 7816 Error Threshold Register 0x1E 8 read-write n 0x0 0x0 RXTHRESHOLD Receive NACK Threshold 0 4 read-write TXTHRESHOLD Transmit NACK Threshold 4 4 read-write 0 TXT asserts on the first NACK that is received. #0000 1 TXT asserts on the second NACK that is received. #0001 IE7816 UART 7816 Interrupt Enable Register 0x19 8 read-write n 0x0 0x0 ADTE ATR Duration Timer Interrupt Enable 3 1 read-write 0 The assertion of IS7816[ADT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[ADT] results in the generation of an interrupt. #1 BWTE Block Wait Timer Interrupt Enable 5 1 read-write 0 The assertion of IS7816[BWT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[BWT] results in the generation of an interrupt. #1 CWTE Character Wait Timer Interrupt Enable 6 1 read-write 0 The assertion of IS7816[CWT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[CWT] results in the generation of an interrupt. #1 GTVE Guard Timer Violated Interrupt Enable 2 1 read-write 0 The assertion of IS7816[GTV] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[GTV] results in the generation of an interrupt. #1 INITDE Initial Character Detected Interrupt Enable 4 1 read-write 0 The assertion of IS7816[INITD] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[INITD] results in the generation of an interrupt. #1 RXTE Receive Threshold Exceeded Interrupt Enable 0 1 read-write 0 The assertion of IS7816[RXT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[RXT] results in the generation of an interrupt. #1 TXTE Transmit Threshold Exceeded Interrupt Enable 1 1 read-write 0 The assertion of IS7816[TXT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[TXT] results in the generation of an interrupt. #1 WTE Wait Timer Interrupt Enable 7 1 read-write 0 The assertion of IS7816[WT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[WT] results in the generation of an interrupt. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 IS7816 UART 7816 Interrupt Status Register 0x1A 8 read-write n 0x0 0x0 ADT ATR Duration Time Interrupt 3 1 read-write 0 ATR Duration time (ADT) has not been violated. #0 1 ATR Duration time (ADT) has been violated. #1 BWT Block Wait Timer Interrupt 5 1 read-write 0 Block wait time (BWT) has not been violated. #0 1 Block wait time (BWT) has been violated. #1 CWT Character Wait Timer Interrupt 6 1 read-write 0 Character wait time (CWT) has not been violated. #0 1 Character wait time (CWT) has been violated. #1 GTV Guard Timer Violated Interrupt 2 1 read-write 0 A guard time (GT, CGT, or BGT) has not been violated. #0 1 A guard time (GT, CGT, or BGT) has been violated. #1 INITD Initial Character Detected Interrupt 4 1 read-write 0 A valid initial character has not been received. #0 1 A valid initial character has been received. #1 RXT Receive Threshold Exceeded Interrupt 0 1 read-write 0 The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD]. #0 1 The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD]. #1 TXT Transmit Threshold Exceeded Interrupt 1 1 read-write 0 The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD]. #0 1 The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD]. #1 WT Wait Timer Interrupt 7 1 read-write 0 Wait time (WT) has not been violated. #0 1 Wait time (WT) has been violated. #1 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. See Hardware flow control #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) Ensure that C2[TE] is asserted before assertion of this bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character detection is disabled. #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TL7816 UART 7816 Transmit Length Register 0x1F 8 read-write n 0x0 0x0 TLEN Transmit Length 0 8 read-write TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write WF7816 UART 7816 Wait FD Register 0x1D 8 read-write n 0x0 0x0 GTFD FD Multiplier 0 8 read-write WGP7816_T1 UART 7816 Wait and Guard Parameter Register 0x3E 8 read-write n 0x0 0x0 BGI Block Guard Time Integer (C7816[TTYPE] = 1) 0 4 read-write CWI1 Character Wait Time Integer 1 (C7816[TTYPE] = 1) 4 4 read-write WN7816 UART 7816 Wait N Register 0x1C 8 read-write n 0x0 0x0 GTN Guard Band N 0 8 read-write WP7816 UART 7816 Wait Parameter Register 0x1B 8 read-write n 0x0 0x0 WTX Wait Time Multiplier (C7816[TTYPE] = 1) 0 8 read-write WP7816A_T0 UART 7816 Wait Parameter Register A UART1 0x3C 8 read-write n 0x0 0x0 WI_H Wait Time Integer High (C7816[TTYPE] = 0) 0 8 read-write WP7816A_T1 UART 7816 Wait Parameter Register A UART1 0x3C 8 read-write n 0x0 0x0 BWI_H Block Wait Time Integer High (C7816[TTYPE] = 1) 0 8 read-write WP7816B_T0 UART 7816 Wait Parameter Register B UART1 0x3D 8 read-write n 0x0 0x0 WI_L Wait Time Integer Low (C7816[TTYPE] = 0) 0 8 read-write WP7816B_T1 UART 7816 Wait Parameter Register B UART1 0x3D 8 read-write n 0x0 0x0 BWI_L Block Wait Time Integer Low (C7816[TTYPE] = 1) 0 8 read-write WP7816C_T1 UART 7816 Wait Parameter Register C 0x3F 8 read-write n 0x0 0x0 CWI2 Character Wait Time Integer 2 (C7816[TTYPE] = 1) 0 5 read-write UART2 Serial Communication Interface UART 0x0 0x0 0x17 registers n UART2_RX_TX 35 UART2_ERR 36 BDH UART Baud Rate Registers: High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt or DMA Request Enable 7 1 read-write 0 LBKDIF interrupt and DMA transfer requests disabled. #0 1 LBKDIF interrupt or DMA transfer requests enabled. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 SBNS Stop Bit Number Select 5 1 read-write 0 Data frame consists of a single stop bit. #0 1 Data frame consists of two stop bits. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 LBKDDMAS LIN Break Detect DMA Select Bit 3 1 read-write 0 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service. #0 1 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer. #1 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY The current received dataword contained in D and C3[R8] was received with noise. 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE The current received dataword contained in D and C3[R8] was received with a parity error. 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. See Hardware flow control #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) Ensure that C2[TE] is asserted before assertion of this bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character detection is disabled. #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write UART3 Serial Communication Interface UART 0x0 0x0 0x17 registers n UART3_RX_TX 44 UART3_ERR 45 BDH UART Baud Rate Registers: High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt or DMA Request Enable 7 1 read-write 0 LBKDIF interrupt and DMA transfer requests disabled. #0 1 LBKDIF interrupt or DMA transfer requests enabled. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 SBNS Stop Bit Number Select 5 1 read-write 0 Data frame consists of a single stop bit. #0 1 Data frame consists of two stop bits. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 LBKDDMAS LIN Break Detect DMA Select Bit 3 1 read-write 0 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service. #0 1 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer. #1 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY The current received dataword contained in D and C3[R8] was received with noise. 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE The current received dataword contained in D and C3[R8] was received with a parity error. 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. See Hardware flow control #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) Ensure that C2[TE] is asserted before assertion of this bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character detection is disabled. #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write UART4 Serial Communication Interface UART 0x0 0x0 0x17 registers n UART4_RX_TX 46 UART4_ERR 47 BDH UART Baud Rate Registers: High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt or DMA Request Enable 7 1 read-write 0 LBKDIF interrupt and DMA transfer requests disabled. #0 1 LBKDIF interrupt or DMA transfer requests enabled. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 SBNS Stop Bit Number Select 5 1 read-write 0 Data frame consists of a single stop bit. #0 1 Data frame consists of two stop bits. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 LBKDDMAS LIN Break Detect DMA Select Bit 3 1 read-write 0 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service. #0 1 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer. #1 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY The current received dataword contained in D and C3[R8] was received with noise. 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE The current received dataword contained in D and C3[R8] was received with a parity error. 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. See Hardware flow control #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) Ensure that C2[TE] is asserted before assertion of this bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character detection is disabled. #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write UART5 Serial Communication Interface UART 0x0 0x0 0x17 registers n UART5_RX_TX 28 UART5_ERR 29 BDH UART Baud Rate Registers: High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt or DMA Request Enable 7 1 read-write 0 LBKDIF interrupt and DMA transfer requests disabled. #0 1 LBKDIF interrupt or DMA transfer requests enabled. #1 RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 SBNS Stop Bit Number Select 5 1 read-write 0 Data frame consists of a single stop bit. #0 1 Data frame consists of two stop bits. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 LBKDDMAS LIN Break Detect DMA Select Bit 3 1 read-write 0 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service. #0 1 If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer. #1 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY The current received dataword contained in D and C3[R8] was received with noise. 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE The current received dataword contained in D and C3[R8] was received with a parity error. 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. See Hardware flow control #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) Ensure that C2[TE] is asserted before assertion of this bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character detection is disabled. #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write WDOG Generation 2008 Watchdog Timer WDOG 0x0 0x0 0x18 registers n WDOG_EWM 22 PRESC Watchdog Prescaler register 0x16 16 read-write n 0x0 0x0 PRESCVAL 3-bit prescaler for the watchdog clock source 8 3 read-write REFRESH Watchdog Refresh register 0xC 16 read-write n 0x0 0x0 WDOGREFRESH Watchdog refresh register 0 16 read-write RSTCNT Watchdog Reset Count register 0x14 16 read-write n 0x0 0x0 RSTCNT Counts the number of times the watchdog resets the system 0 16 read-write STCTRLH Watchdog Status and Control Register High 0x0 16 read-write n 0x0 0x0 ALLOWUPDATE Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window (WCT) closes, through unlock sequence 4 1 read-write 0 No further updates allowed to WDOG write-once registers. #0 1 WDOG write-once registers can be unlocked for updating. #1 BYTESEL This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode. 12 2 read-write 00 Byte 0 selected #00 01 Byte 1 selected #01 10 Byte 2 selected #10 11 Byte 3 selected #11 CLKSRC Selects clock source for the WDOG timer and other internal timing operations. 1 1 read-write 0 WDOG clock sourced from LPO . #0 1 WDOG clock sourced from alternate clock source. #1 DBGEN Enables or disables WDOG in Debug mode. 5 1 read-write 0 WDOG is disabled in CPU Debug mode. #0 1 WDOG is enabled in CPU Debug mode. #1 DISTESTWDOG Allows the WDOG's functional test mode to be disabled permanently 14 1 read-write 0 WDOG functional test mode is not disabled. #0 1 WDOG functional test mode is disabled permanently until reset. #1 IRQRSTEN Used to enable the debug breadcrumbs feature 2 1 read-write 0 WDOG time-out generates reset only. #0 1 WDOG time-out initially generates an interrupt. After WCT, it generates a reset. #1 STOPEN Enables or disables WDOG in Stop mode. 6 1 read-write 0 WDOG is disabled in CPU Stop mode. #0 1 WDOG is enabled in CPU Stop mode. #1 TESTSEL Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer. 11 1 read-write 0 Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. #0 1 Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing. #1 TESTWDOG Puts the watchdog in the functional test mode 10 1 read-write WAITEN Enables or disables WDOG in Wait mode. 7 1 read-write 0 WDOG is disabled in CPU Wait mode. #0 1 WDOG is enabled in CPU Wait mode. #1 WDOGEN Enables or disables the WDOG's operation 0 1 read-write 0 WDOG is disabled. #0 1 WDOG is enabled. #1 WINEN Enables Windowing mode. 3 1 read-write 0 Windowing mode is disabled. #0 1 Windowing mode is enabled. #1 STCTRLL Watchdog Status and Control Register Low 0x2 16 read-write n 0x0 0x0 INTFLG Interrupt flag 15 1 read-write TMROUTH Watchdog Timer Output Register High 0x10 16 read-write n 0x0 0x0 TIMEROUTHIGH Shows the value of the upper 16 bits of the watchdog timer. 0 16 read-write TMROUTL Watchdog Timer Output Register Low 0x12 16 read-write n 0x0 0x0 TIMEROUTLOW Shows the value of the lower 16 bits of the watchdog timer. 0 16 read-write TOVALH Watchdog Time-out Value Register High 0x4 16 read-write n 0x0 0x0 TOVALHIGH Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer 0 16 read-write TOVALL Watchdog Time-out Value Register Low 0x6 16 read-write n 0x0 0x0 TOVALLOW Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer 0 16 read-write UNLOCK Watchdog Unlock register 0xE 16 read-write n 0x0 0x0 WDOGUNLOCK Writing the unlock sequence values to this register to makes the watchdog write-once registers writable again 0 16 read-write WINH Watchdog Window Register High 0x8 16 read-write n 0x0 0x0 WINHIGH Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog 0 16 read-write WINL Watchdog Window Register Low 0xA 16 read-write n 0x0 0x0 WINLOW Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog 0 16 read-write XBARA Crossbar Switch XBARA 0x0 0x0 0x40 registers n XBARA 54 CTRL0 Crossbar A Control Register 0 0x3C 16 read-write n 0x0 0x0 DEN0 DMA Enable for XBAR_OUT0 0 1 read-write 0 DMA disabled #0 1 DMA enabled #1 DEN1 DMA Enable for XBAR_OUT1 8 1 read-write 0 DMA disabled #0 1 DMA enabled #1 EDGE0 Active edge for edge detection on XBAR_OUT0 2 2 read-write 00 STS0 never asserts #00 01 STS0 asserts on rising edges of XBAR_OUT0 #01 10 STS0 asserts on falling edges of XBAR_OUT0 #10 11 STS0 asserts on rising and falling edges of XBAR_OUT0 #11 EDGE1 Active edge for edge detection on XBAR_OUT1 10 2 read-write 00 STS1 never asserts #00 01 STS1 asserts on rising edges of XBAR_OUT1 #01 10 STS1 asserts on falling edges of XBAR_OUT1 #10 11 STS1 asserts on rising and falling edges of XBAR_OUT1 #11 IEN0 Interrupt Enable for XBAR_OUT0 1 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 IEN1 Interrupt Enable for XBAR_OUT1 9 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 STS0 Edge detection status for XBAR_OUT0 4 1 read-write 0 Active edge not yet detected on XBAR_OUT0 #0 1 Active edge detected on XBAR_OUT0 #1 STS1 Edge detection status for XBAR_OUT1 12 1 read-write 0 Active edge not yet detected on XBAR_OUT1 #0 1 Active edge detected on XBAR_OUT1 #1 CTRL1 Crossbar A Control Register 1 0x3E 16 read-write n 0x0 0x0 DEN2 DMA Enable for XBAR_OUT2 0 1 read-write 0 DMA disabled #0 1 DMA enabled #1 DEN3 DMA Enable for XBAR_OUT3 8 1 read-write 0 DMA disabled #0 1 DMA enabled #1 EDGE2 Active edge for edge detection on XBAR_OUT2 2 2 read-write 00 STS2 never asserts #00 01 STS2 asserts on rising edges of XBAR_OUT2 #01 10 STS2 asserts on falling edges of XBAR_OUT2 #10 11 STS2 asserts on rising and falling edges of XBAR_OUT2 #11 EDGE3 Active edge for edge detection on XBAR_OUT3 10 2 read-write 00 STS3 never asserts #00 01 STS3 asserts on rising edges of XBAR_OUT3 #01 10 STS3 asserts on falling edges of XBAR_OUT3 #10 11 STS3 asserts on rising and falling edges of XBAR_OUT3 #11 IEN2 Interrupt Enable for XBAR_OUT2 1 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 IEN3 Interrupt Enable for XBAR_OUT3 9 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 STS2 Edge detection status for XBAR_OUT2 4 1 read-write 0 Active edge not yet detected on XBAR_OUT2 #0 1 Active edge detected on XBAR_OUT2 #1 STS3 Edge detection status for XBAR_OUT3 12 1 read-write 0 Active edge not yet detected on XBAR_OUT3 #0 1 Active edge detected on XBAR_OUT3 #1 SEL0 Crossbar A Select Register 0 0x0 16 read-write n 0x0 0x0 SEL0 Input (XBARA_INn) to be muxed to XBARA_OUT0 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL1 Input (XBARA_INn) to be muxed to XBARA_OUT1 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL1 Crossbar A Select Register 1 0x2 16 read-write n 0x0 0x0 SEL2 Input (XBARA_INn) to be muxed to XBARA_OUT2 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL3 Input (XBARA_INn) to be muxed to XBARA_OUT3 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL10 Crossbar A Select Register 10 0x14 16 read-write n 0x0 0x0 SEL20 Input (XBARA_INn) to be muxed to XBARA_OUT20 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL21 Input (XBARA_INn) to be muxed to XBARA_OUT21 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL11 Crossbar A Select Register 11 0x16 16 read-write n 0x0 0x0 SEL22 Input (XBARA_INn) to be muxed to XBARA_OUT22 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL23 Input (XBARA_INn) to be muxed to XBARA_OUT23 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL12 Crossbar A Select Register 12 0x18 16 read-write n 0x0 0x0 SEL24 Input (XBARA_INn) to be muxed to XBARA_OUT24 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL25 Input (XBARA_INn) to be muxed to XBARA_OUT25 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL13 Crossbar A Select Register 13 0x1A 16 read-write n 0x0 0x0 SEL26 Input (XBARA_INn) to be muxed to XBARA_OUT26 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL27 Input (XBARA_INn) to be muxed to XBARA_OUT27 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL14 Crossbar A Select Register 14 0x1C 16 read-write n 0x0 0x0 SEL28 Input (XBARA_INn) to be muxed to XBARA_OUT28 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL29 Input (XBARA_INn) to be muxed to XBARA_OUT29 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL15 Crossbar A Select Register 15 0x1E 16 read-write n 0x0 0x0 SEL30 Input (XBARA_INn) to be muxed to XBARA_OUT30 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL31 Input (XBARA_INn) to be muxed to XBARA_OUT31 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL16 Crossbar A Select Register 16 0x20 16 read-write n 0x0 0x0 SEL32 Input (XBARA_INn) to be muxed to XBARA_OUT32 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL33 Input (XBARA_INn) to be muxed to XBARA_OUT33 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL17 Crossbar A Select Register 17 0x22 16 read-write n 0x0 0x0 SEL34 Input (XBARA_INn) to be muxed to XBARA_OUT34 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL35 Input (XBARA_INn) to be muxed to XBARA_OUT35 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL18 Crossbar A Select Register 18 0x24 16 read-write n 0x0 0x0 SEL36 Input (XBARA_INn) to be muxed to XBARA_OUT36 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL37 Input (XBARA_INn) to be muxed to XBARA_OUT37 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL19 Crossbar A Select Register 19 0x26 16 read-write n 0x0 0x0 SEL38 Input (XBARA_INn) to be muxed to XBARA_OUT38 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL39 Input (XBARA_INn) to be muxed to XBARA_OUT39 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL2 Crossbar A Select Register 2 0x4 16 read-write n 0x0 0x0 SEL4 Input (XBARA_INn) to be muxed to XBARA_OUT4 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL5 Input (XBARA_INn) to be muxed to XBARA_OUT5 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL20 Crossbar A Select Register 20 0x28 16 read-write n 0x0 0x0 SEL40 Input (XBARA_INn) to be muxed to XBARA_OUT40 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL41 Input (XBARA_INn) to be muxed to XBARA_OUT41 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL21 Crossbar A Select Register 21 0x2A 16 read-write n 0x0 0x0 SEL42 Input (XBARA_INn) to be muxed to XBARA_OUT42 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL43 Input (XBARA_INn) to be muxed to XBARA_OUT43 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL22 Crossbar A Select Register 22 0x2C 16 read-write n 0x0 0x0 SEL44 Input (XBARA_INn) to be muxed to XBARA_OUT44 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL45 Input (XBARA_INn) to be muxed to XBARA_OUT45 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL23 Crossbar A Select Register 23 0x2E 16 read-write n 0x0 0x0 SEL46 Input (XBARA_INn) to be muxed to XBARA_OUT46 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL47 Input (XBARA_INn) to be muxed to XBARA_OUT47 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL24 Crossbar A Select Register 24 0x30 16 read-write n 0x0 0x0 SEL48 Input (XBARA_INn) to be muxed to XBARA_OUT48 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL49 Input (XBARA_INn) to be muxed to XBARA_OUT49 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL25 Crossbar A Select Register 25 0x32 16 read-write n 0x0 0x0 SEL50 Input (XBARA_INn) to be muxed to XBARA_OUT50 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL51 Input (XBARA_INn) to be muxed to XBARA_OUT51 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL26 Crossbar A Select Register 26 0x34 16 read-write n 0x0 0x0 SEL52 Input (XBARA_INn) to be muxed to XBARA_OUT52 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL53 Input (XBARA_INn) to be muxed to XBARA_OUT53 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL27 Crossbar A Select Register 27 0x36 16 read-write n 0x0 0x0 SEL54 Input (XBARA_INn) to be muxed to XBARA_OUT54 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL55 Input (XBARA_INn) to be muxed to XBARA_OUT55 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL28 Crossbar A Select Register 28 0x38 16 read-write n 0x0 0x0 SEL56 Input (XBARA_INn) to be muxed to XBARA_OUT56 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL57 Input (XBARA_INn) to be muxed to XBARA_OUT57 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL29 Crossbar A Select Register 29 0x3A 16 read-write n 0x0 0x0 SEL58 Input (XBARA_INn) to be muxed to XBARA_OUT58 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL3 Crossbar A Select Register 3 0x6 16 read-write n 0x0 0x0 SEL6 Input (XBARA_INn) to be muxed to XBARA_OUT6 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL7 Input (XBARA_INn) to be muxed to XBARA_OUT7 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL4 Crossbar A Select Register 4 0x8 16 read-write n 0x0 0x0 SEL8 Input (XBARA_INn) to be muxed to XBARA_OUT8 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL9 Input (XBARA_INn) to be muxed to XBARA_OUT9 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL5 Crossbar A Select Register 5 0xA 16 read-write n 0x0 0x0 SEL10 Input (XBARA_INn) to be muxed to XBARA_OUT10 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL11 Input (XBARA_INn) to be muxed to XBARA_OUT11 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL6 Crossbar A Select Register 6 0xC 16 read-write n 0x0 0x0 SEL12 Input (XBARA_INn) to be muxed to XBARA_OUT12 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL13 Input (XBARA_INn) to be muxed to XBARA_OUT13 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL7 Crossbar A Select Register 7 0xE 16 read-write n 0x0 0x0 SEL14 Input (XBARA_INn) to be muxed to XBARA_OUT14 (refer to Functional Description section for input/output assignment) 0 6 read-write SEL15 Input (XBARA_INn) to be muxed to XBARA_OUT15 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL8 Crossbar A Select Register 8 0x10 16 read-write n 0x0 0x0 SEL16 Input (XBARA_INn) to be muxed to XBARA_OUT16 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL17 Input (XBARA_INn) to be muxed to XBARA_OUT17 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL9 Crossbar A Select Register 9 0x12 16 read-write n 0x0 0x0 SEL18 Input (XBARA_INn) to be muxed to XBARA_OUT18 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 SEL19 Input (XBARA_INn) to be muxed to XBARA_OUT19 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 Logic zero #0 1 Logic one #1 2 XBAR0_IN2 input pin #10 4 XBAR0_IN4 input pin #100 8 XBAR0_IN8 input pin #1000 16 FTM0 all channels output compare ORed together #10000 32 High Speed Analog-to-Digital Converter 1 conversion A complete #100000 33 High Speed Analog-to-Digital Converter 0 conversion A complete #100001 17 FTM0 all channels counter init ORed together #10001 34 High Speed Analog-to-Digital Converter 1 conversion B complete #100010 35 High Speed Analog-to-Digital Converter 0 conversion B complete #100011 9 XBAR0_IN9 input pin #1001 18 FTM3 all channels output compare ORed together #10010 36 FTM1 all channels output compare ORed together #100100 37 FTM1 all channels counter init ORed together #100101 19 FTM3 all channels counter init ORed together #10011 38 DMA channel 0 done #100110 39 DMA channel 1 done #100111 5 XBAR0_IN5 input pin #101 10 XBAR0_IN10 input pin #1010 20 PWMA channel 0 trigger 0 #10100 40 DMA channel 6 done #101000 41 DMA channel 7 done #101001 21 PWMA channel 0 trigger 1 #10101 42 PIT trigger 0 #101010 43 PIT trigger 1 #101011 11 XBAR0_IN11 input pin #1011 22 PWMA channel 1 trigger 0 #10110 44 Analog-to-Digital Converter 0 conversion complete #101100 45 ENC compare trigger and position match #101101 23 PWMA channel 1 trigger 1 #10111 46 AOI output 0 #101110 47 AOI output 1 #101111 3 XBAR0_IN3 input pin #11 6 XBAR0_IN6 input pin #110 12 CMP0 Output #1100 24 PWMA channel 2 trigger 0 #11000 48 AOI output 2 #110000 49 AOI output 3 #110001 25 PWMA channel 2 trigger 1 #11001 50 PIT trigger 2 #110010 51 PIT trigger 3 #110011 13 CMP1 Output #1101 26 PWMA channel 3 trigger 0 #11010 52 PWMB channel 0 trigger 0 or trigger 1 #110100 53 PWMB channel 1 trigger 0 or trigger 1 #110101 27 PWMA channel 3 trigger 1 #11011 54 PWMB channel 2 trigger 0 or trigger 1 #110110 55 PWMB channel 3 trigger 0 or trigger 1 #110111 7 XBAR0_IN7 input pin #111 14 CMP2 Output #1110 28 PDB0 channel 1 output trigger #11100 56 FTM2 all channels output compare ORed together #111000 57 FTM2 all channels counter init ORed together #111001 29 PDB0 channel 0 output trigger #11101 15 CMP3 Output #1111 30 PDB1 channel 1 output trigger #11110 31 PDB1 channel 0 output trigger #11111 XBARB Crossbar Switch XBARB 0x0 0x0 0x10 registers n SEL0 Crossbar B Select Register 0 0x0 16 read-write n 0x0 0x0 SEL0 Input (XBARB_INn) to be muxed to XBARB_OUT0 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL1 Input (XBARB_INn) to be muxed to XBARB_OUT1 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL1 Crossbar B Select Register 1 0x2 16 read-write n 0x0 0x0 SEL2 Input (XBARB_INn) to be muxed to XBARB_OUT2 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL3 Input (XBARB_INn) to be muxed to XBARB_OUT3 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL2 Crossbar B Select Register 2 0x4 16 read-write n 0x0 0x0 SEL4 Input (XBARB_INn) to be muxed to XBARB_OUT4 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL5 Input (XBARB_INn) to be muxed to XBARB_OUT5 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL3 Crossbar B Select Register 3 0x6 16 read-write n 0x0 0x0 SEL6 Input (XBARB_INn) to be muxed to XBARB_OUT6 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL7 Input (XBARB_INn) to be muxed to XBARB_OUT7 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL4 Crossbar B Select Register 4 0x8 16 read-write n 0x0 0x0 SEL8 Input (XBARB_INn) to be muxed to XBARB_OUT8 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL9 Input (XBARB_INn) to be muxed to XBARB_OUT9 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL5 Crossbar B Select Register 5 0xA 16 read-write n 0x0 0x0 SEL10 Input (XBARB_INn) to be muxed to XBARB_OUT10 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL11 Input (XBARB_INn) to be muxed to XBARB_OUT11 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL6 Crossbar B Select Register 6 0xC 16 read-write n 0x0 0x0 SEL12 Input (XBARB_INn) to be muxed to XBARB_OUT12 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL13 Input (XBARB_INn) to be muxed to XBARB_OUT13 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL7 Crossbar B Select Register 7 0xE 16 read-write n 0x0 0x0 SEL14 Input (XBARB_INn) to be muxed to XBARB_OUT14 (refer to Functional Description section for input/output assignment) 0 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111 SEL15 Input (XBARB_INn) to be muxed to XBARB_OUT15 (refer to Functional Description section for input/output assignment) 8 6 read-write 0 CMP0 Output #0 1 CMP1 Output #1 2 CMP2 Output #10 4 FTM0 all channels output compare ORed together #100 8 PWMA channel 0 trigger 0 #1000 16 FTM1 all channels output compare ORed together #10000 32 FTM2 all channels output compare ORed together #100000 33 FTM2 all channels counter init ORed together #100001 17 FTM1 all channels counter init ORed together #10001 34 PDB0 channel 1 output trigger #100010 35 PDB1 channel 1 output trigger #100011 9 PWMA channel 1 trigger 0 #1001 18 DMA channel 0 done #10010 36 High Speed Analog-to-Digital Converter 1 conversion A complete #100100 37 High Speed Analog-to-Digital Converter 1 conversion B complete #100101 19 DMA channel 1 done #10011 38 Analog-to-Digital Converter 0 conversion complete #100110 5 FTM0 all channels counter init ORed together #101 10 PWMA channel 2 trigger 0 #1010 20 XBAR0_IN10 input pin #10100 21 XBAR0_IN11 input pin #10101 11 PWMA channel 3 trigger 0 #1011 22 DMA channel 6 done #10110 23 DMA channel 7 done #10111 3 CMP3 Output #11 6 FTM3 all channels output compare ORed together #110 12 PDB0 channel 0 output trigger #1100 24 PIT trigger 0 #11000 25 PIT trigger 1 #11001 13 High Speed Analog-to-Digital Converter 0 conversion A complete #1101 26 PDB1 channel 0 output trigger #11010 27 High Speed Analog-to-Digital Converter 0 conversion B complete #11011 7 FTM3 all channels counter init ORed together #111 14 XBAR0_IN2 input pin #1110 28 PWMB channel 0 trigger 0 or trigger 1 #11100 29 PWMB channel 1 trigger 0 or trigger 1 #11101 15 XBAR0_IN3 input pin #1111 30 PWMB channel 2 trigger 0 or trigger 1 #11110 31 PWMB channel 3 trigger 0 or trigger 1 #11111